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參數(shù)資料
| 型號(hào)： | 932S203YFLN |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, GREEN, MO-118, SSOP-56 |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 243K |
| 代理商： | 932S203YFLN |
IDTTM Frequency Generator with 133MHz Differential CPU Clocks
0601G—01/26/10
ICS932S203
Frequency Generator with 133MHz Differential CPU Clocks
14
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no
defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard
skew described below as Tpci.
Un-Buffered Mode 3V66 & PCI Phase Relationship
3V66 (1:0)
3V66 (4:2)
3V66_5
PCICLK_F (2:0) PCICLK (6:0)
Tpci
Group Skews at Common Transition Edges: (Un-Buffered Mode)
GROUP
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
3V66
3V66 (5:0) pin to pin skew
0
500
ps
PCI
PCI_F (2:0) and PCI (6:0) pin to pin skew
0
500
ps
3V66 to PCI
S3V66-PCI
3V66 (5:0) leads 33MHz PCI
1.5
3.5
ns
1Guaranteed by design, not 100% tested in production.
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low
in their next high to low transition.
PCI_STOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
Assertion of PCI_STOP# Waveforms
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 932S208DG | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 932S208DGLFT | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 932S208DGT | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 932S208DFLF | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 932S208DFT | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 932S203YFLXT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Frequency Generator with 133MHz Differential CPU Clocks |
| 932S203YGLXT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Frequency Generator with 133MHz Differential CPU Clocks |
| 932S208DFLF | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 SERVER MAIN CLOCK RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 932S208DFLFT | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 SERVER MAIN CLOCK RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 932S208DGLF | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 SERVER MAIN CLOCK RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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