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參數(shù)資料
| 型號(hào)： | 9328DMQB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual 8-Bit Shift Register |
| 中文描述： | 93 SERIES, 8-BIT RIGHT SERIAL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 126K |
| 代理商： | 9328DMQB |
Electrical Characteristics
Over Recommended Operating Free Air Temperature Range (Unless Otherwise Noted) (Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 1)
I
OS
Short Circuit
Output Current
V
CC
e
Max
(Note 2)
MIL
b
20
b
70
mA
COMM
b
20
b
70
I
CC
Note 1:
All typicals are at V
CC
e
5V, T
A
e
25
§
C.
Note 2:
Not more than one output should be shorted at a time.
Supply Current
V
CC
e
Max
77
mA
Switching Characteristics
V
CC
e a
5.0V, T
A
e a
25
§
C (See Section 1 for waveforms and load configurations)
C
L
e
15 pF
R
L
e
400
X
Symbol
Parameter
Units
Min
Max
f
max
Maximum Shift Right Frequency
20
MHz
t
PLH
t
PHL
Propagation Delay
CP to Q7 or Q7
20
35
ns
t
PHL
Propagation Delay MR to Q7
50
ns
Functional Description
The two 8-bit shift registers have a common clock input (pin
9) and separate clock inputs (pins 10 and 7). The clocking
of each register is controlled by the OR function of the sep-
arate and the common clock input. Each register is com-
posed of eight clocked RS master/slave flip-flops and a
number of gates. The clock OR gate drives the eight clock
inputs of the flip-flops in parallel. When the two clock inputs
(the separate and the common) to the OR gate are LOW,
the slave latches are steady, but data can enter the master
latches via the R and S input. During the first LOW-to-HIGH
transition of either, or both simultaneously, of the two clock
inputs, the data inputs (R and S) are inhibited so that a later
change in input data will not affect the master; then the now
trapped information in the master is transferred to the slave.
When the transfer is complete, both the master and the
slave are steady as long as either or both clock inputs re-
main HIGH. During the HIGH-to-LOW transition of the last
remaining HIGH clock input, the transfer path from master
to slave is inhibited first, leaving the slave steady in its pres-
ent state. The data inputs (R and S) are enabled so that new
data can enter the master. Either of the clock inputs can be
used as clock inhibit inputs by applying a logic HIGH signal.
Each 8-bit shift register has a 2-input multiplexer in front of
the serial data input. The two data inputs D0 and D1 are
controlled by the data select input (S) following the Boolean
expression:
Serial data in: S
D
e
SD0
a
SD1
An asynchronous master reset is provided which, when acti-
vated by a LOW logic level, will clear all 16 stages indepen-
dently of any other input signal.
Shift Select Table
INPUTS
OUTPUT
S
D0
D1
Q7 (t
n
a
8
)
L
L
H
H
L
H
X
X
X
X
L
H
L
H
L
H
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
n
a
8
e
indicates state after eight clock pulse
3
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