參數(shù)資料
型號(hào): 9308DMQB
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 鎖存器
英文描述: 93 SERIES, DUAL LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP24
封裝: CERAMIC, DIP-24
文件頁(yè)數(shù): 3/6頁(yè)
文件大?。?/td> 121K
代理商: 9308DMQB
Functional Description
Data can be entered into the latch when both of the enable
inputs are LOW As long as this logic condition exists the
output of the latch will follow the input If either of the enable
inputs goes HIGH the data present in the latch at that time
is held in the latch and is no longer affected by data input
The master reset overrides all other input conditions and
forces the outputs of all the latches LOW when a LOW sig-
nal is applied to the Master Reset input
Truth Table
MR
E0E1
D
Qn
Operation
H
L
Data Entry
H
L
H
Data Entry
HL
H
X
Qnb1
Hold
HH
L
X
Qnb1
Hold
HH
H
X
Qnb1
Hold
L
X
L
Reset
Qnb1 e Previous Output State
Qn e Present Output State
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Logic Diagram
TLF10208 – 3
Switching Characteristics VCC ea50V TA ea25 C (See Section 5 for test waveforms and output load)
9308
Symbol
Parameter
CL e 15 pF
Units
RL e 400X
Min
Max
tPLH
Propagation Delay
30
ns
tPHL
EntoQn
22
tPLH
Propagation Delay
15
ns
tPHL
Dn to Qn
18
tPHL
Propagation Delay
22
ns
MR to Qn
3
相關(guān)PDF資料
PDF描述
9308FMQB 93 SERIES, DUAL LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDFP24
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930920-G30 BARRIER STRIP TERMINAL BLOCK
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