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參數(shù)資料
| 型號： | 92HD73E2X5NDGXC1X |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 編解碼器 |
| 英文描述： | PCM CODEC, QCC40 |
| 封裝： | 5 X 5 MM, 0.40 MM PITCH, ROHS COMPLIANT, QFN-40 |
| 文件頁數(shù)： | 2/237頁 |
| 文件大?。?/td> | 2843K |
| 代理商： | 92HD73E2X5NDGXC1X |
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10
V 1.3 08/11
2011 INTEGRATED DEVICE TECHNOLOGY, INC.
92HD73E
Ten Channel HD Audio Codec
1.3.9.1.
AFG D0
The AFG D0 state is the active state for the device. All functions are active if their power state (if they
support power management at their node level) has been set to D0.
1.3.9.2.
AFG D1
D1 is a lower power mode where all converter widgets are disabled. Analog mixer and port functions
are active.
1.3.9.3.
AFG D2
The D2 state further reduces power by disabling the mixer and port functions. The port amplifiers
and internal references remain active to keep port coupling caps charged and the system ready for a
quick resume to either the D1 or D0 state.
1.3.9.4.
AFG D3
The D3-default state is available for HD Audio compliance. All converters are shut down. Port ampli-
fiers and references are active but in a low power state to prevent pops. Resume times may be lon-
ger than those from D2, but still very fast to meet Intel low power goals.
The traditional use for D3 was as a transitional state before power was removed (D3 cold) before the
system entered into standby, hibernate, or shut-down. To conserve power, Intel now promotes using
D3 whenever there are no active streams or other activity that requires the part to consume full
power. The system remains in S0 during this time. When a stream request or user activity requires
the CODEC to become active, the driver will immediately transition the CODEC from D3 to D0. To
enable this use model, the CODEC must resume within 10mS and not pop.
The default power state for the Audio Function Group after reset is D3-default
1.3.9.5.
AFG D3 and vendor specific verbs
The programmable values, exposed via vendor-specific settings, are under the IDT Device Driver
control for further power reduction.
1.3.10. Low-voltage HDA Signaling
The 92HD73E is compatible with either 1.5V or 3.3V HDA bus signaling; the voltage selection is
done dynamically based on the input voltage of DVDD_IO on the 48QFP package. The 40QFN
allows for 3.3V only.
When in 1.5V mode, the 92HD73E can correctly decode BITCLK, SYNC, RESET# and SDO as they
operate at 1.5V; additionally it will drive SDI and SDO at 1.5V. None of the GPIOs are affected, as
they always function at their nominal voltage (DVDD or AVDD).
1.3.11. Multi-channel capture
The capability to assign multiple ADC “Input Converters” to the same stream is supported to meet
the microphone array requirements of Vista and future operating systems. Single converter streams
are still supported and is done by assigning unique non zero Stream IDs to each converter. All cap-
3.VAG is always ramped up and down gradually, except in the case of a sudden power removal. VAG is active in D2/D3 but in
a low power state.
4. BITCLK must be active and both AVDD and DVDD must be available for Port Sense to operate.
5.Vendor specific bit for Ref Top controls VAG generator, Bandgap Reference, and Reference bias generator. Place part into
D3 and power down all ports (using vendor specific verbs) before powering down Ref Top.
6.Obviously not active if BITCLK is not running (Controller in D3).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 92HD73E2X5NDGXC1X8 | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| 92HD75B1X5NLGXYAX | 制造商:Integrated Device Technology Inc 功能描述:92HD75B1X5NLGXYAX - Bulk |
| 92HD75B1X5NLGXYAX8 | 制造商:Integrated Device Technology Inc 功能描述:AUD CODEC 2ADC / 2DAC 24BIT 32PIN VFQFPN - Tape and Reel |
| 92HD75B1X5NLGXZAX | 制造商:Integrated Device Technology Inc 功能描述:AUD CODEC 2ADC / 2DAC 24BIT 32PIN VFQFPN - Bulk |
| 92HD75B1X5NLGXZAX8 | 制造商:Integrated Device Technology Inc 功能描述:92HD75B1X5NLGXZAX8 - Tape and Reel |
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