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參數(shù)資料
| 型號(hào)： | 9248DF-39LFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, GREEN, SSOP-48 |
| 文件頁數(shù)： | 13/18頁 |
| 文件大?。?/td> | 321K |
| 代理商： | 9248DF-39LFT |
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Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note: PWD = Power-Up Default
Note 1. Default at Power-up will be for latched logic inputs to define frequency. Bits 4, 5, 6
are default to 000, and if bit 3 is written to a 1 to use Bits 6:4, then these should be
defined to desired frequency at same write cycle.
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