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參數(shù)資料
| 型號： | 9248DF-39LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, GREEN, SSOP-48 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 321K |
| 代理商： | 9248DF-39LF |
5
ICS9248- 39
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
t
i
B#
n
i
PD
W
Pn
o
i
t
p
i
r
c
s
e
D
7
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
6
t
i
B7
1
)
t
c
a
n
I
/
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A
(
F
_
K
L
C
I
C
P
5
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
4
t
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B3
11
)
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n
I
/
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A
(
4
K
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P
3
t
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B2
11
)
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3
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2
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2
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B8
1
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0
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L
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P
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
t
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B#
n
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PD
W
Pn
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t
p
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7
t
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B-
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#
2
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6
t
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B-
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5
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4
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3
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41
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41
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Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
t
i
B#
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PD
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Pn
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t
p
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7
t
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1
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(
6
t
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B-
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#
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5
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21
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8
4
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21
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4
2
3
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2
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(
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3
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S
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