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參數(shù)資料
| 型號： | 9248AG-192 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封裝： | 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-28 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 201K |
| 代理商： | 9248AG-192 |
5
ICS9248-192
0540F—10/27/05
Bit2
Bit7
Bit6
Bit5
Bit4
FS4
FS3
FS2
FS1
FS0
00
0
60
30
-0.4 % down spread
00
1
60
30
-0.6 % down spread
00
01
0
60
30
-0.8 % down spread
00
01
1
60
30
-1.0 % down spread
00
10
0
66.6
33.3
-0.4 % down spread
00
10
1
66.6
33.3
-0.6 % down spread
00
11
0
66.6
33.3
-0.8 % down spread
00
11
1
66.6
33.3
-1.0 % down spread
01
00
0
67.32
33.66
2% over-clocking
01
00
1
68.64
34.32
4% over-clocking
01
0
69.96
34.98
6% over-clocking
01
1
72.6
36.3
10% over-clocking
01
10
0
61.5
30.75
over-clocking
01
10
1
63
31.5
over-clocking
01
11
0
64
32
over-clocking
01
11
1
65
32.5
over-clocking
Bit
10
00
0
60
30
+/- 0.5% center spread
2,7:4
10
00
1
66.6
33.3
+/- 0.5% center spread
10
01
0
50
25
under-clocking
10
01
1
48
24
under-clocking
10
0
58.8
29.4
2% under-clock
10
1
57.6
28.8
4% under-clock
10
11
0
56.4
28.2
6% under-clock
10
11
1
54
27
10% under-clock
11
00
0
60
30
-1.4 % down spread
11
00
1
60
30
-1.6 % down spread
11
01
0
60
30
-1.8 % down spread
11
01
1
60
30
-2.0 % down spread
11
10
0
66.6
33.3
-1.4 % down spread
11
10
1
66.6
33.3
-1.6 % down spread
11
0
66.6
33.3
-1.8 % down spread
11
1
66.6
33.3
-2.0 % down spread
Hardware latch inputs can only access these frequencies
0-Frequency is seleced by hardware select. Latched input
Bit1
0-Normal
1-Spread spectrun Enabled
0
Bit0
0-Running 1-Tristate all outputs
0
PWD
Bit
Bit3
0
00000
CPU
PCI
Spread %
1-Frequency is seleced by Bit 2, 7:4
Note: PWD = Power-Up Default
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 051-453-0000 | RF Coaxial Connectors |
| 9248AG-92LFT | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 9248BF-138 | 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 9248BF-138LFT | 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 9248BF-55 | 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9248AG-192LF | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 9248AG192LFT | 制造商:ICS 功能描述: |
| 9248AG-192LFT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 9248AG-198LF | 制造商:Integrated Device Technology Inc 功能描述:9248AG-198LF - Bulk |
| 9248AG-92LF | 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK GEN DUAL 48TSSOP - Rail/Tube |
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