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參數(shù)資料
| 型號： | 9248AG-150LNT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48 |
| 文件頁數(shù)： | 12/13頁 |
| 文件大?。?/td> | 175K |
| 代理商： | 9248AG-150LNT |
8
ICS9248-150
0352G—08/04/06
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering
down the clock synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven
to a low value and held prior to turning off the VCOs and crystal. The power down latency should be as short as possible
but conforming to the sequence requirements shown below.
Notes:
1. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock.
CPUCLKT
CPUCLKC
VCO
Crystal
PD#
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PDF描述 |
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| 9248AG-150LN | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
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| 9248AG-192 | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 051-453-0000 | RF Coaxial Connectors |
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