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參數(shù)資料
| 型號(hào)： | 9159N-05 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁(yè)數(shù)： | 3/7頁(yè) |
| 文件大?。?/td> | 228K |
| 代理商： | 9159N-05 |
3
ICS9159-05
Pin Descriptions
Note:
1. Internally pulled-up
PIN
NUMBER
PIN NAME
TYPE
DESCRIPTION
8, 20, 26
VDD
PWR
Power for logic, CPU and fixed frequency output buffers.
1X1
IN
XTAL or external reference frequency input. This input includes XTAL load
capacitance and feedback bias for a 4-20 MHz XTAL, normally 14.318 MHz.
2
X2
OUT
XTAL output which includes XTAL load capacitance.
3, 11, 23, 17
GND
PWR
Ground for logic, CPU and fixed frequency output buffers.
6, 7, 9
CPU(0:2)
OUT
Processor clock outputs which are a multiple of the input reference frequency as
shown in the table.
4, 5
FS(0:1)
IN
Frequency multiplier select pins. See table below. These inputs have internal pull-
up devices.
10
ECPU
OUT
Early CPU clock. Transition precedes CPU clocks.
15, 16, 18,
19,21, 22
BUS(0:5)
OUT
Bus clock outputs are fixed at 1/2 the PCLK frequency.
12
DOZE#
1
IN
Doze mode control. Reduces CPU and BUS clock frequencies by 1/2 when low.
13
BSEL#
1
IN
BUS select for BSEL = 0, BUS = CPU/2
for BSEL = 1, BUS = CPU
14
STOP#
1
Stop Clock. Stops all CPU clock outputs and forces them to a logic low level
synchronously with their next low level transition.
24
KEYBD
OUT
12 MHz fixed clock (with 14.318 MHz input).
25
DISK
OUT
24 MHz fixed clock (with 14.318 MHz input).
27, 28
REF (0:1)
OUT
REF is a buffered copy of the crystal oscillator or reference input clock,
nominally 14.31818 MHz.
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