參數(shù)資料
型號: 9147F-12
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: 0.300 INCH, SSOP-48
文件頁數(shù): 2/9頁
文件大?。?/td> 497K
代理商: 9147F-12
2
ICS9147-12
Pin Descriptions
Note 1:Internal pull-up resistor of nomimally 100K to 120K at 3.3V on indicated inputs.
Note 2: The PD# input pin has a protection diode clamp to the VDDL power supply. If VDDL is not connected to VDD, (ie
VDDL=2.5V, VDD=3.3V) then this input must have a series resistor if the logic high is connected to VDD. This input
series resistor provides current limit for the clamp diode. For a pullup to VDD it should be 1Kohm or more from the PD#
pin to VDD. If the PD# pin is being driven by logic powered by 3.3V, then a 100 series resistor will be suffcient.
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
FS2
IN
Latched input for frequency select2
1
REF1
OUT
Reference clock output
2
REF0
OUT
Reference clock output
3, 10, 17, 24, 31,
31, 37, 43
GND
PWR
Ground (common)
4X1
IN
Crystal or reference input, nominally 14.318 MHz. Includes
internal load cap to GND and feedback resistor from X2.
5
X2
OUT
Crystal output, includes internal load cap to GND.
6, 20,
N/C
-
Pins are not internally connected
7, 15
VDD2
PWR
Supply for PCICLK_F, and PCICLK (0:5)
8
PCICLK_F
OUT
Free running PCI clock
9, 11, 12, 13, 14, 16
PCICLK (0:5)
OUT
PCI clocks
18
FS0
IN
Frequency select 0 input1
19
FS1
IN
Frequency select 1 input
1
21
VDD4
PWR
Supply for 48MHz and 24MHz clocks
22
48MHz
OUT
48MHz driver output for USB clock
23
24MHz
OUT
24MHz driver output for Super I/O clock
25, 28,34
VDD3
PWR
Supply for SDRAM (0:7),
26, 27, 29, 30,
32, 33, 35, 36
SDRAM (0:7)
OUT
SDRAMs clock at CPU speed
38, 39, 41, 42
CPUCLK (0:3)
OUT
CPUCLK clock output, powered by VDDL
40, 46
VDDL
PWR
Supply for CPUCLK (0:3) & IOAPIC
44
PD#
IN
Power down stops all clocks low and disables oscillator and
internal VCO’s.2
45
IOAPIC
OUT
IOAPIC clock output, powered by VDDL at crystal frequency
47
REF2
OUT
Reference clock output.
48
VDD1
PWR
Supply for REF (0:2), X1, X2
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