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參數(shù)資料
| 型號： | 89LV55 |
| 廠商： | Atmel Corp. |
| 英文描述： | 8-Bit Microcontroller with 20K Bytes Flash |
| 中文描述： | 8位閃存微控制器20,000字節(jié) |
| 文件頁數(shù)： | 18/23頁 |
| 文件大?。?/td> | 595K |
| 代理商： | 89LV55 |
AT89LV55
4-210
AC Characteristics
Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other
outputs = 80 pF.
External Program and Data Memory Characteristics
Symbol
Parameter
12 MHz Oscillator
Variable Oscillator
Units
Min
Max
Min
Max
1/t
CLCL
Oscillator Frequency
0
12
MHz
t
LHLL
ALE Pulse Width
127
2t
CLCL
- 40
ns
t
AVLL
Address Valid to ALE Low
43
t
CLCL
- 40
ns
t
LLAX
Address Hold After ALE Low
48
t
CLCL
- 35
ns
t
LLIV
ALE Low to Valid Instruction In
233
4t
CLCL
- 100
ns
t
LLPL
ALE Low to PSEN Low
43
t
CLCL
- 40
ns
t
PLPH
PSEN Pulse Width
205
3t
CLCL
- 45
ns
t
PLIV
PSEN Low to Valid Instruction In
145
3t
CLCL
- 105
ns
t
PXIX
Input Instruction Hold After PSEN
0
0
ns
t
PXIZ
Input Instruction Float After PSEN
59
t
CLCL
- 25
ns
t
PXAV
t
AVIV
PSEN to Address Valid
75
t
CLCL
- 8
ns
Address to Valid Instruction In
312
5t
CLCL
- 105
ns
t
PLAZ
PSEN Low to Address Float
10
10
ns
t
RLRH
t
WLWH
RD Pulse Width
400
6t
CLCL
- 100
6t
CLCL
- 100
ns
WR Pulse Width
400
ns
t
RLDV
RD Low to Valid Data In
252
5t
CLCL
- 165
ns
t
RHDX
t
RHDZ
Data Hold After RD
0
0
ns
Data Float After RD
97
2t
CLCL
- 70
ns
t
LLDV
ALE Low to Valid Data In
517
8t
CLCL
- 150
ns
t
AVDV
t
LLWL
Address to Valid Data In
585
9t
CLCL
- 165
3t
CLCL
+ 50
ns
ALE Low to RD or WR Low
200
300
3t
CLCL
- 50
ns
t
AVWL
Address to RD or WR Low
203
4t
CLCL
- 130
ns
t
QVWX
t
QVWH
Data Valid to WR Transition
23
t
CLCL
- 60
7t
CLCL
- 150
ns
Data Valid to WR High
433
ns
t
WHQX
Data Hold After WR
33
t
CLCL
- 50
ns
t
RLAZ
RD Low to Address Float
0
0
ns
t
WHLH
RD or WR High to ALE High
43
123
t
CLCL
- 40
t
CLCL
+ 40
ns
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