- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376479 > 89LS8252 (Atmel Corp.) 8-Bit Microcontroller with 8K Bytes Flash PDF資料下載
參數(shù)資料
| 型號(hào)： | 89LS8252 |
| 廠商： | Atmel Corp. |
| 英文描述： | 8-Bit Microcontroller with 8K Bytes Flash |
| 中文描述： | 8位具有8K字節(jié)的閃存，微控制器 |
| 文件頁數(shù)： | 16/31頁 |
| 文件大小： | 470K |
| 代理商： | 89LS8252 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
AT89LS8252
4-152
Interrupts
The AT89LS8252 has a total of six interrupt vectors: two
external interrupts (INT0 and INT1), three timer interrupts
(Timers 0, 1, and 2), and the serial port interrupt. These
interrupts are all shown in Figure 10.
Each of these interrupt sources can be individually enabled
or disabled by setting or clearing a bit in Special Function
Register IE. IE also contains a global disable bit, EA, which
disables all interrupts at once.
Note that Table 10 shows that bit position IE.6 is unimple-
mented. In the AT89C51 and AT89LV51, bit position IE.5 is
also unimplemented. User software should not write 1s to
these bit positions, since they may be used in future AT89
products.
Timer 2 interrupt is generated by the logical OR of bits TF2
and EXF2 in register T2CON. Neither of these flags is
cleared by hardware when the service routine is vectored
to. In fact, the service routine may have to determine
whether it was TF2 or EXF2 that generated the interrupt,
and that bit will have to be cleared in software.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at
S5P2 of the cycle in which the timers overflow. The values
are then polled by the circuitry in the next cycle. However,
the Timer 2 flag, TF2, is set at S2P2 and is polled in the
same cycle in which the timer overflows.
Figure 9.
SPI Transfer Format with CPHA = 1
*Not defined but normally LSB of previously transmitted character
MSB
6
5
4
3
2
1
LSB
1
2
3
4
5
6
7
8
MSB
*
6
5
4
3
2
1
LSB
SCK CYCLE #
(FOR REFERENCE)
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
(FROM MASTER)
MISO
(FROM SLAVE)
SS (TO SLAVE)
Figure 10.
Interrupt Sources
Table 10.
Interrupt Enable (IE) Register
(MSB)
(LSB)
EA
—
ET2
ES
ET1
EX1
ET0
EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables the interrupt.
Symbol
Position
Function
EA
IE.7
Disables all interrupts. If EA = 0, no interrupt
is acknowledged. If EA = 1, each interrupt
source is individually enabled or disabled by
setting or clearing its enable bit.
—
IE.6
Reserved.
ET2
IE.5
Timer 2 interrupt enable bit.
ES
IE.4
SPI and UART interrupt enable bit.
ET1
IE.3
Timer 1 interrupt enable bit.
EX1
IE.2
External interrupt 1 enable bit.
ET0
IE.1
Timer 0 interrupt enable bit.
EX0
IE.0
External interrupt 0 enable bit.
User software should never write 1s to unimplemented bits, because
they may be used in future AT89 products.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 89LV55 | 8-Bit Microcontroller with 20K Bytes Flash |
| 89S8252 | 8-Bit Microcontroller with 8K Bytes Flash |
| 8M052489 | 8m Class DC to AC Inverter |
| 8T26A | 8-Channel, 10-Bit ADC with I2C Compatible Interface in 20-Lead TSSOP; Package: TSSOP; No of Pins: 20; Temperature Range: Industrial |
| 8T95 | 8-Channel, 10-Bit ADC with I2C Compatible Interface in 20-Lead TSSOP; Package: TSSOP; No of Pins: 20; Temperature Range: Industrial |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 89LV1632 | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:16 Megabit (512K x 32-Bit) Low Voltage MCM SRAM |
| 89LV1632RPQE-30 | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:16 Megabit (512K x 32-Bit) Low Voltage MCM SRAM |
| 89LV1632RPQH-30 | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:16 Megabit (512K x 32-Bit) Low Voltage MCM SRAM |
| 89LV1632RPQI-30 | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:16 Megabit (512K x 32-Bit) Low Voltage MCM SRAM |
| 89LV1632RPQK-30 | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:16 Megabit (512K x 32-Bit) Low Voltage MCM SRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。