參數(shù)資料
型號： 89HPES8T5AZBBC
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA196
封裝： 15 X 15 MM, 1 MM PITCH, CABGA-196
文件頁數(shù)： 27/29頁
文件大?。?/td> 622K
代理商： 89HPES8T5AZBBC
7 of 29
May 7, 2009
IDT 89HPES8T5A Data Sheet
RSTHALT
I
Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, the PES8T5A executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device opera-
tion begins. The device exits the reset state when the RSTHALT bit is
cleared in the PA_SWCTL register by an SMBus master.
SWMODE[2:0]
I
Switch Mode. These configuration pins determine the PES8T5A switch
operating mode.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 - through 0xF Reserved
WAKEN
I/O
Wake Input/Output. The WAKEN signal is an input or output. The WAKEN
signal input/output selection can be made through the WAKEDIR bit setting
in the WAKEUPCNTL register.
Signal
Type
Name/Description
JTAG_TCK
I
JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG_TDI
I
JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
JTAG_TDO
O
JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG_TMS
I
JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG_TRST_N
I
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 6 Test Pins
Signal
Type
Name/Description
VDDCORE
I
Core VDD. Power supply for core logic.
VDDIO
I
I/O VDD. LVTTL I/O buffer power supply.
VDDPE
I
PCI Express Digital Power. PCI Express digital power used by the digital
power of the SerDes.
VDDAPE
I
PCI Express Analog Power. PCI Express analog power used by the PLL
and bias generator.
VTTPE
I
PCI Express Termination Power.
VSS
I
Ground.
Table 7 Power and Ground Pins
Signal
Type
Name/Description
Table 5 System Pins (Part 2 of 2)
相關(guān)PDF資料
PDF描述
89RW30 SCR
89RW40 SCR
8AF4NLV 50 A, 400 V, SILICON, RECTIFIER DIODE
8C443 PIN/Preamp(Datacom, Telecom)
8C447 PIN/Preamp(Datacom, General Purpose, Analog Applications)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
89HPES8T5AZBBC8 功能描述:接口-I/O擴展器 RoHS:否 制造商:NXP Semiconductors 邏輯系列: 輸入/輸出端數(shù)量: 最大工作頻率:100 kHz 工作電源電壓:1.65 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HVQFN-16 封裝:Reel
89HPES8T5AZBBCG 功能描述:接口-I/O擴展器 RoHS:否 制造商:NXP Semiconductors 邏輯系列: 輸入/輸出端數(shù)量: 最大工作頻率:100 kHz 工作電源電壓:1.65 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HVQFN-16 封裝:Reel
89HPES8T5AZBBCG8 功能描述:接口-I/O擴展器 RoHS:否 制造商:NXP Semiconductors 邏輯系列: 輸入/輸出端數(shù)量: 最大工作頻率:100 kHz 工作電源電壓:1.65 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HVQFN-16 封裝:Reel
89HPES8T5AZBBCGI 功能描述:接口-I/O擴展器 RoHS:否 制造商:NXP Semiconductors 邏輯系列: 輸入/輸出端數(shù)量: 最大工作頻率:100 kHz 工作電源電壓:1.65 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HVQFN-16 封裝:Reel
89HPES8T5AZBBCGI8 制造商:Integrated Device Technology Inc 功能描述:PCI Express Switch I/O Expansion Switch 8Lanes 5Ports 1-CH 196-Pin CABGA 制造商:Integrated Device Technology Inc 功能描述:8-LANE 5-PORT PCI EXPRESS? SWITCH - Tape and Reel
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*