參數(shù)資料
型號: 89HPES16T4G2ZBBXG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA288
封裝: 23 X 23 MM, 1 MM PITCH, GREEN, SBGA-288
文件頁數(shù): 29/31頁
文件大?。?/td> 580K
代理商: 89HPES16T4G2ZBBXG
7 of 31
September 13, 2010
IDT 89HPES16T4G2 Data Sheet
Signal
Type
Name/Description
JTAG_TCK
I
JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG_TDI
I
JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
JTAG_TDO
O
JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG_TMS
I
JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG_TRST_N
I
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 6 Test Pins
Signal
Type
Name/Description
REFRES0
I/O
Port 0 External Reference Resistor. Provides a reference for the Port 0
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
REFRES2
I/O
Port 2 External Reference Resistor. Provides a reference for the Port 2
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
REFRES4
I/O
Port 4 External Reference Resistor. Provides a reference for the Port 4
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
REFRES6
I/O
Port 6 External Reference Resistor. Provides a reference for the Port 6
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
VDDCORE
I
Core VDD. Power supply for core logic.
VDDI/O
I
I/O VDD. LVTTL I/O buffer power supply.
VDDPEA
I
PCI Express Analog Power. Serdes analog power supply (1.0V).
VDDPEHA
I
PCI Express Analog High Power. Serdes analog power supply (2.5V).
VDDPETA
I
PCI Express Transmitter Analog Voltage. Serdes transmitter analog
power supply (1.0V).
VSS
I
Ground.
Table 7 Power, Ground, and SerDes Resistor Pins
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