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參數(shù)資料
| 型號(hào)： | 8817 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | NTSC/PAL Digital Video Encoder |
| 中文描述： | NTSC / PAL數(shù)字視頻編碼器 |
| 文件頁(yè)數(shù)： | 4/43頁(yè) |
| 文件大小： | 818K |
| 代理商： | 8817 |
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ASAHI KASEI
[AK8817]
MS0413-E-00
4
2005 / Aug
Pin Functional Description
Pin#
Pin Name
I/O
Functional Outline
G2
CLKIN
I
Clock input pin.
Input a clock which is synchronized with data.
When to input 601 data : 27 MHz.
When to input square pixel data : 24.5454 MHz ( NTSC )/ 29.50 MHz ( PAL )
Internal clock is inverted (internal operation timing edge is inverted.)
Connect to either DVDD or DGND.
Power Down Pin. After returning from PD mode to normal operation, RESET
Sequence should be done to AK8817.
“L “(GND level): Power-down
“H “: normal operation
Reset input pin. In order to initialize the device , an initialization must be made in
accordance with the reset sequence.
“L “ : reset
“H “ : normal operation
Hi-Z input is acceptable to this pin at PDN = L.
I2C data pin.
This pin is pulled-up to PVDD.
Hi-Z input is possible when PDN is at low.
SDA input is not accepted during the reset sequence operation.
I2C clock input pin
An input level of lower-than-PVDD should be input.
Hi-Z input is possible when PDN is at low.
SCL input is not accepted during the reset sequence operation.
Data Video Signal input pin (MSB).
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin (LSB).
Hi-Z input is acceptable to this pin at PDN = L.
Horizontal SYNC signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Vertical SYNC signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
On-chip VREF output pin.
AVSS level is output on this pin at PDN = L.
Connect this pin to Analog Ground via a 0.1 uF or larger capacitor.
IREF output pin. Connect this pin to Analog ground via a 12k ohm resistor
( better than +/- 1% accuracy ).
DAC output pin. Connect this pin to Analog ground via a 390 ohm resistor
( better than +/- 1% accuracy ).
Video output pin.
SAG Compensation Input pin
Analog power supply pin.
Analog ground pin.
Digital power supply pin (digital core power supply).
Digital ground pin (digital core ground).
Power supply pin for chip pad.
Ground pin for PVDD.
Substrate ground pin.
Connect this pin to Analog ground
F1
CLKINV
I
B5
PDN
I
A6
RSTN
I
C7
SDA
I
B6
SCL
I
F4
D7
I
G4
D6
I
F5
D5
I
G5
D4
I
F6
D3
I
G6
D2
I
F7
D1
I
E6
D0
I
C6
HDI
I
D7
VDI
I
C1
VREF
O
C2
IREF
O
A2
DACOUT
O
A4
A3
B1
B2
VOUT
SAG
AVDD
AVSS
DVDD
DVSS
PVDD
PVSS
O
O
P
G
P
G
P
G
A5, G3
B4, F3
E7
D6
B3
BVSS
G
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