
Advance Information
82C205
912-1000-024
Page 20
Revision 1.0
7
6
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0
Index 0Ah -0Ch
Reserved
Default = 00h
Index 0Dh
OSD Start Address (R/W)
Default = 00h
Starting address of OSD Index Buffer Low Byte
Index 0Eh
Default = 00h
Starting address of OSD Index Buffer Middle Byte
Index 0Fh
Default = 00h
Reserved
Reserved
Starting address of OSD Index Buffer High Byte
Index 10h
Display Panel Start Address – Field 1 (R/W)
Default = 00h
Starting address for Display buffer.
This is the starting address for field 1 of the TV or VGA data.
Low Byte
Index 11h
Default = 00h
Middle Byte
Index 12h
Default = 00h
Reserved
Reserved
High Byte
Index 13h
Display Panel Start Address – Field 2 (R/W)
Default = 00h
Starting address for Display buffer.
This is the starting address for field 2 of the TV data.
Low Byte
Index 14h
Default = 00h
Middle Byte
Index 15h
Default = 00h
Reserved
Reserved
High Byte
Index 16h
Video Pitch (R/W)
Default = 00h
Pitch of the Frame Buffer.
Low Byte
Index 17h
Default = 00h
Reserved
Reserved
Reserved
High Byte
Index 18h - 19h
Reserved
Default = 00h
Index 1Ah
OSD Pitch (R/W)
Default = 00h
Pitch of the OSD Index Buffer
Low Byte
Index 1Bh
Default = 00h
Reserved
Reserved
Reserved
High Byte
Index 1Ch
Memory Bank (R/W)
Default = 00h
Bank Address for DRAM access by CPU.
The CPU address is structured so that the resultant memory address is:
bank[7:0], cpu_addr[21:14]
Hence, each bank is 16Kbytes, with 256 available banks.