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| 型號(hào)： | 821INSTSET |
| 英文描述： | MPC821 PowerPC Instruction Set |
| 中文描述： | MPC821 PowerPC指令集 |
| 文件頁(yè)數(shù)： | 55/186頁(yè) |
| 文件大?。?/td> | 748K |
| 代理商： | 821INSTSET |
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Motorola
MPCxxx INSTRUCTION SET
55
eieio
Enforce In-Order Execution of I/O
eieio
The
eieio
instruction provides an ordering function for the effects of load and store
instructions executed by a processor. These loads and stores are divided into two sets,
which are ordered separately. The memory accessescaused by a
dcbz
instruction are
ordered like a store. The two sets follow:
1. Loads and stores to memory that is both caching-inhibited and guarded, and stores
to memory that is write-through required.
The
eieio
instruction controls the order in which the accesses are performed in
main memory. It ensures that all applicable memory accesses caused by
instructions preceding the
eieio
instruction have completed with respect to main
memory before any applicable memory accesses caused by instructions following
the
eieio
instruction access main memory. It acts like a barrier that flows through
the memory queues and to main memory, preventing the reordering of memory
accesses across the barrier. No ordering is performed for
dcbz
if the instruction
causes the system alignment error handler to be invoked.
All accesses in this set are ordered as a single set—that is, there is not one order
for loads and stores to caching-inhibited and guarded memory and another order
for stores to write-through required memory.
2. Stores to memory that have all of the following attributes—caching-allowed, write-
through not required, and memory-coherency required.
The
eieio
instruction controls the order in which the accesses are performed with
respect to coherent memory. It ensures that all applicable stores caused by
instructions preceding the
eieio
instruction have completed with respect to
coherent memory before any applicable stores caused by instructions following the
eieio
instruction complete with respect to coherent memory.
With the exception of
dcbz
,
eieio
does not affect the order of cache operations (whether
caused explicitly by execution of a cache management instruction, or implicitly by the
cache coherencymechanism). The
eieio
instruction does not affect the order of accesses
in one set with respect to accesses in the other set.
The
eieio
instruction may complete before memory accesses caused by instructions
preceding the
eieio
instruction have been performed with respect to main memory or
coherent memory as appropriate.
The
eieio
instruction is intended for use in managing shared data structures, in accessing
memory-mapped I/O, and in preventing load/store combining operations in main memory.
For the first use, the shared data structure and the lock that protects it must be altered
only by stores that are in the same set (1 or 2; see previous discussion). For the second
use,
eieio
can be thought of as placing a barrier into the stream of memory accesses
0
5 6
10 11
15 16
20 21
30 31
Reserved
31
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
854
0
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| 821K002-173L401 | 功能描述:2 Position Circular Connector Plug, Male Pins Solder Cup Gold 制造商:norcomp inc. 系列:821K 包裝:托盤 零件狀態(tài):在售 連接器類型:插頭，公引腳 針腳數(shù):2 外殼尺寸 - 插件:- 外殼尺寸，MIL:- 安裝類型:自由懸掛 端接:焊杯 緊固類型:推挽式 朝向:帶標(biāo)記 侵入防護(hù):IP67 - 防塵，防水 外殼材料，鍍層:黃銅，鍍鎳 觸頭鍍層:金 特性:后殼，屏蔽式，防拉線扣 觸頭鍍層厚度:7μin（0.18μm） 額定電流:- 電壓 - 額定:- 工作溫度:-40°C ~ 200°C 標(biāo)準(zhǔn)包裝:1 |
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