參數(shù)資料
型號(hào): 8102805PX
元件分類: 光電耦合器
英文描述: 2 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 10 Mbps
封裝: HERMETIC SEALED, DIP-8
文件頁數(shù): 12/12頁
文件大?。?/td> 448K
代理商: 8102805PX
9
Notes:
1. Eachchannel.
2. All devices are considered two-terminal devices; I
I-O is measured between all input leads or terminals shorted together and all output
leadsorterminalsshortedtogether.
3. Measuredbetweeneachinputpairshortedtogetherandalloutputconnectionsforthatchannelshortedtogether.
4. Measuredbetweenadjacentinputpairsshortedtogetherforeachmultichanneldevice.
5. t
PHL propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.5V point on the leading edge of
the output pulse.The t
PLH propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.5 V point
onthetrailingedgeoftheoutputpulse.
6. TheHCPL-6630,HCPL-6631,andHCPL-663Kdualchannelpartsfunctionastwoindependentsinglechannelunits.Usethesinglechannel
parameterlimitsforeachchannel.
7. CM
L is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state
(V
O<0.8 V). CMH is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic
highstate(V
O > 2.0V).
8. Thisisamomentarywithstandtest,notanoperatingcondition.
9. Itisessentialthatabypasscapacitor(0.01to0.1F,ceramic)beconnectedfromV
CC to ground. Total lead length between both ends of
thisexternalcapacitorandtheisolatorconnectionsshouldnotexceed20mm.
10. Noexternalpullupisrequiredforahighlogicstateontheenableinput.
11. Thet
ELH enable propagation delay is measured from the 1.5 V point on the trailing edge of the enable input pulse to the 1.5 V point on
thetrailingedgeoftheoutputpulse.
12. Thet
EHL enable propagation delay is measured from the 1.5 V point on the leading edge of the enable input pulse to the 1.5 V point on
theleadingedgeoftheoutputpulse.
13. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD and 883B parts receive 100% testing at 25, 125, and -55°C (Sub-
groups1and9,2and10,3and11,respectively).
14. Parametersaretestedaspartofdeviceinitialcharacterizationandafterdesignandprocesschanges.Parametersareguaranteedtolimits
specifiedforalllotsnotspecificallytested.
15. Notrequiredfor6N134,6N134/883B,8102801,HCPL-268Kand5962-9800101types.
16. Requiredfor6N134,6N134/883B,8102801,HCPL-268Kand5962-9800101types.
17. NotrequiredforHCPL-5650,HCPL-5651and8102805types.
18. RequiredforHCPL-5650,HCPL-5651and8102805typesonly.
Figure 1. High Level Output Current vs. Tempera-
ture.
Figure 2. Input-Output Characteristics.
Figure 3. Input Diode Forward Characteristics.
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