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參數(shù)資料
| 型號： | 80RIA120M |
| 廠商： | VISHAY SEMICONDUCTORS |
| 元件分類： | 晶閘管 |
| 英文描述： | 125 A, 1200 V, SCR, TO-209AC |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 191K |
| 代理商： | 80RIA120M |
80RIA Series
23
3
di/dt
Max. non-repetitive rate of rise
T
J
= 125°C, Vd = rated V
DRM
, I
TM
= 2xdi/dt snubber
of turned-on current
300
A/s
0.2F, 15
, Gate pulse: 20V, 65, t
p
= 6s, t
r
= 0.5s
Per JEDEC Standard RS-397, 5.2.2.6.
Gate pulse: 10V, 15
source, t
p
= 6s, t
r
= 0.1s,
Vd = rated VDRM, I
TM
= 50Adc, T
J = 25°C.
I
TM
= 50A, T
J
= T
J
max, di/dt = -5A/s min., V
R
= 50V,
dv/dt = 20V/s, Gate bias: 0V 25
, t
p
= 500s
dv/dt
Maximum critical rate of rise of
off-state voltage
I
RRM
Max. peak reverse and off-state
I
DRM
leakage current
Blocking
Parameter
80RIA
Units
Conditions
15
mA
T
J
= 125°C rated V
DRM
/V
RRM
applied
P
GM
Maximum peak gate power
12
T
J
= T
J
max, t
p ≤
5ms
P
G(AV)
Maximum average gate power
3
T
J
= T
J
max, f = 50Hz, d% = 50
I
GM
Max. peak positive gate current
3
A
T
J
= T
J
max, t
p ≤
5ms
+V
GM
Maximum peak positive
gate voltage
-V
GM
Maximum peak negative
gate voltage
I
GT
Max. DC gate current required
270
T
J
= - 40°C
to trigger
120
mA
T
J
= 25°C
60
T
J
= 125°C
V
GT
Max. DC gate voltage required
3.5
T
J
= - 40°C
to trigger
2.5
V
T
J
= 25°C
1.5
T
J
= 125°C
I
GD
DC gate current not to trigger
6
mA
Parameter
80RIA
Units
Conditions
Triggering
W
20
10
VT
J
= T
J
max, t
p ≤
5ms
V
GD
DC gate voltage not to trigger
0.25
V
Max. gate current/ voltage not to
trigger is the max. value which
will not trigger any unit with rated
V
DRM
anode-to-cathode applied
T
J
= T
J
max
Max. required gate trigger/ cur-
rent/ voltage are the lowest value
which will trigger all units 6V an-
ode-to-cathode applied
Parameter
80RIA
Units
Conditions
Switching
s
500
V/ s
T
J
= 125°C exponential to 67% rated V
DRM
t
d
Typical delay time
1
t
q
Typical turn-off time
110
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