參數(shù)資料
型號： 80C300
元件分類： DC/DC變換器
英文描述： Hi-Freq DC-DC Converter, 0C to +70C, 8-PDIP, TUBE
中文描述： 80C300 10/100快速以太網(wǎng)控制器手冊1 / 98
文件頁數(shù)： 1/55頁
文件大小： 588K
代理商： 80C300
4-1
1
MD400145/G
98012
80C300
Full Duplex CMOS Ethernet
10/100 Mega Bit/Sec Data Link Controller
Features
I
Low Power CMOS Technology
I
10/100 MBit Ethernet Controller Optimized for
Switching Hub, Multiport Bridge/Router, &
Server Applications
I
Meets ANSI/IEEE 802.3 and ISO 8802-3 Standards
for Ethernet (10Base-5) Thin Net (10Base-2)
(10Base-T) and the Proposed 100Base-T4,
100Base-TX Standards
I
10 MHz Serial/Parallel Conversion in 10 MBit/sec
Serial Mode.
I
Standard 10MBit/sec Serial Mode or
Programmable MII Ethernet Interface for 10/100
MBit/sec Applications
I
Programmability of Double Word Threshold
Count for Space Available/Data Available Ready
Condition for Transmit/Receive FIFOs
I
Auto Retransmit Upon Collision Sense
I
Preamble Generation and Removal
I
Automatic 32-Bit FCS (CRC) Generation and
Checking
I
Collision Handling, Transmission Deferral and
Retransmission with Automatic Jam and
Backoff Functions
I
Error Interrupt and Status Generation
I
Selectable Little Endian/Big Endian Transmit Byte
Ordering for FIFO Interface for Intel/Motorola
Compatibility
I
Single 5 V
±
5% Power Supply
I
Standard CPU and Peripheral Interface
Control Signals
I
128/128 Byte ndependent Transmit/Receive FIFOs
with 32 Bit Data Path Interface
- 1 G Bits/sec (133 M Bytes/sec) Peak Data Rate
in 32 Bit Mode.
I
Loopback Capability for Diagnostics
I
32 Bit FIFO Data Path
Hurricane is a trademark of SEEQ Technology Inc.
I
Inputs and Outputs TTL Compatible
I
The Following Additional Features can be
Programmed for the 80C300
- 64 bit Multicast Filter
- Reports Status of “SQE” During Transmits
- Transmit No CRC Mode
- Transmit No Preamble Mode
- Transmit Packet Autopadding Mode
- Receive CRC Mode
- Disable Self-Receive on Transmit Mode
- Disable Further Transmissions when Both
Transmit Status Registers are Full
- Disable Loading the Transmit Status for
Successfully Transmitted Packets
- Disable the Receive Interrupts Independent
of the Receive Command Register Setting
- Successful Packet Transmit Completion
Feature
I
Full Duplex Operation
- Provides 20/200 Mbps Bandwidthfor
Switched Networks
- Supports AutoDUPLEX Mode for Automatic
Full Duplex Operation
I
Transmit Status on a Per Packet Basis Reports the
Following
- Occurrence of a Transmit FIFO Underflow
- Transmit Collision Occurrence
- 16 Collision Occurrence
- Carrier Sense Error During Transmission
- 10/100 Mbit/sec Transmit Clock Detect
- Late Collision Occurrence
- Transmission Successful
- Transmission Deferred
Full Duplex
HURRICANE
TM
Note: Check for latest Data Sheet revision
before starting any designs.
SEEQ Data Sheets are now on the Web, at
www.lsilogic.com.
This document is an LSI Logic document. Any
reference to SEEQ Technology should be
considered LSI Logic.
相關(guān)PDF資料
PDF描述
80C300 Full Duplex CMOS Ethernet 10/100 Mega Bit/Sec Data Link Controller(全雙工CMOS以太網(wǎng) 10/100 MB/S數(shù)據(jù)鏈路控制器)
80C31X CMOS single-chip 8-bit microcontrollers
80C32-L16 CMOS 0 to 44 MHz Single Chip 8?bit Microntroller
80C32 80C51 8-bit microcontroller family 8K.64K/256.1K OTP/ROM/ROMless, low voltage 2.7V.5.5V, low power, high speed 33 MHz
80C32 CMOS 0 to 44 MHz Single-chip 8 Bit Microcontroller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
80C31 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless low voltage 2.7V.5.5V, low power, high speed 33 MHz
80C31BH 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
80C31BH/BQA 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
80C31BH1 制造商:Intel 功能描述:
80C31BH-1 制造商: 功能描述: 制造商:undefined 功能描述:
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