參數(shù)資料
型號(hào): 7LVC544APWDH
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: Octal D-type registered transceiver, inverting 3-State
中文描述: LVC/LCX/Z SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24
文件頁(yè)數(shù): 7/10頁(yè)
文件大?。?/td> 90K
代理商: 7LVC544APWDH
Philips Semiconductors
Octal D-type registered transceiver, inverting
(3-State)
Product specification
74LVC544A
1998 Jul 29
7
AC WAVEFORMS
V
M
= 1.5V at V
CC
V
M
= 0.5V * V
CC
at V
CC
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
V
X
= V
OL
+ 0.3V at V
CC
2.7V
V
X
= V
OL
+ 0.1V
CC
at V
CC
<
2.7V
V
Y
= V
OH
– 0.3V at V
CC
2.7V
V
Y
= V
OH
– 0.1V
CC
at V
CC
<
2.7V
2.7V
2.7V
A
, B
n
INPUT
V
M
t
PHL
t
PLH
V
OL
V
I
V
M
GND
V
OH
B
, A
OUTPUT
SV00737
Figure 1. Input (An, Bn) to output (Bn, An) propagation delays.
t
w
t
PHL
t
PLH
LE
XX
INPUT
A
, B
OUTPUT
V
OL
V
M
V
M
V
M
V
M
V
M
V
I
GND
V
OH
SV00738
Figure 2. Latch enable input (LEXX) pulse width, the latch
enable input to output (An, Bn) propagation delays.
t
PLZ
t
PZL
V
I
OE
, E
XX
INPUT
GND
V
CC
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
OL
V
OH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
outputs
enabled
outputs
enabled
outputs
disabled
t
PHZ
V
M
V
M
V
M
t
PZH
V
X
V
Y
SW00210
Figure 3. 3-State enable and disable times
ééé
ééé
ééééééééé
ééééééééé
ééééééééé
th
th
V
M
A
, B
n
INPUT
V
M
LE
, E
XX
INPUT
GND
t
SU
NOTE:
The shaded areas indicate when the input is permitted to change
for predictable output performance.
t
SU
V
I
GND
V
I
SV00739
Figure 4. Data set-up and hold times for the (An, Bn) input to
the LEXX and EXX inputs
TEST CIRCUIT
PULSE
GENERATOR
V
I
R
T
D.U.T.
V
O
C
L
50pF
S
1
2 x V
CC
Open
GND
500
500
V
CC
V
I
2.7V
V
CC
2.7V
2.7V – 3.6V
Test
S
1
GND
t
PLZ
/t
PZL
t
PHZ
/t
PZH
2 x V
CC
t
PLH
/t
PHL
Open
SY00003
V
CC
Figure 5. Load circuitry for switching times
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