參數(shù)資料
型號(hào)： 7C425-30
廠(chǎng)商： Cypress Semiconductor Corp.
英文描述： 256/512/1K/2K/4K x 9 Asynchronous FIFO
中文描述： 256/512/1K/2K/4K × 9異步FIFO
文件頁(yè)數(shù)： 11/22頁(yè)
文件大小： 522K
代理商： 7C425-30
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *A
Page 11 of 22
Architecture
The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9,
CY7C432/3 FIFOs consist of an array of 256, 512, 1024, 2048,
4096 words of 9 bits each (implemented by an array of du-
al-port RAM cells), a read pointer, a write pointer, control sig-
nals (W, R, XI, XO, FL, RT, MR), and Full, Half Full, and Empty
flags.
Dual-Port RAM
The dual-port RAM architecture refers to the basic memory
cell used in the RAM. The cell itself enables the read and write
operations to be independent of each other, which is neces-
sary to achieve truly asynchronous operation of the inputs and
outputs. A second benefit is that the time required to increment
the read and write pointers is much less than the time that
would be required for data propagation through the memory,
which would be the case if the memory were implemented
using the conventional register array architecture.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Master Reset
(MR) cycle. This causes the FIFO to enter the empty condition
signified by the Empty flag (EF) being LOW, and both the Half
Full (HF) and Full flags (FF) being HIGH. Read (R) and write
(W) must be HIGH t
RPW
/t
WPW
before and t
RMR
after the rising
edge of MR for a valid reset cycle. If reading from the FIFO
after a reset cycle is attempted, the outputs will all be in the
high-impedance state.
Note:
15. Expansion Out of device 1 (XO
1
) is connected to Expansion In of device 2 (XI
2
).
Switching Waveforms
(continued)
ExpansionTiming Diagrams
C420
–
17
R
W
XO
1
(XI
2
)
D
0
–
D
8
DATA VALID
DATA
VALID
DATA
VALID
t
XOL
t
XOH
t
HD
t
SD
t
SD
t
HD
t
XOL
t
LZR
t
A
t
DVR
t
XOH
t
A
t
DVR
t
HZR
XO
1
(XI
2
)
Q
0
–
Q
8
WRITE TO LAST PHYSICAL
LOCATION OF DEVICE 1
WRITE TO FIRST PHYSICAL
LOCATION OF DEVICE 2
READ FROM LAST PHYSICAL
LOCATION OF DEVICE 1
READ FROM FIRST PHYSICAL
LOCATION OF DEVICE 2
C420
–
18
t
WR
t
RR
DATA VALID
[15]
[15]
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
7C425-40 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:256/512/1K/2K/4K x 9 Asynchronous FIFO
7C425-65 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:256/512/1K/2K/4K x 9 Asynchronous FIFO
7C4261NCC 制造商:Cypress Semiconductor 功能描述:
7C4265CC 制造商:Cypress Semiconductor 功能描述:
7C4271CC 制造商:Cypress Semiconductor 功能描述:
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