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參數(shù)資料
| 型號： | 7C420-25 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256/512/1K/2K/4K x 9 Asynchronous FIFO |
| 中文描述： | 256/512/1K/2K/4K × 9異步FIFO |
| 文件頁數(shù)： | 11/22頁 |
| 文件大?。?/td> | 522K |
| 代理商： | 7C420-25 |
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *A
Page 11 of 22
Architecture
The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9,
CY7C432/3 FIFOs consist of an array of 256, 512, 1024, 2048,
4096 words of 9 bits each (implemented by an array of du-
al-port RAM cells), a read pointer, a write pointer, control sig-
nals (W, R, XI, XO, FL, RT, MR), and Full, Half Full, and Empty
flags.
Dual-Port RAM
The dual-port RAM architecture refers to the basic memory
cell used in the RAM. The cell itself enables the read and write
operations to be independent of each other, which is neces-
sary to achieve truly asynchronous operation of the inputs and
outputs. A second benefit is that the time required to increment
the read and write pointers is much less than the time that
would be required for data propagation through the memory,
which would be the case if the memory were implemented
using the conventional register array architecture.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Master Reset
(MR) cycle. This causes the FIFO to enter the empty condition
signified by the Empty flag (EF) being LOW, and both the Half
Full (HF) and Full flags (FF) being HIGH. Read (R) and write
(W) must be HIGH t
RPW
/t
WPW
before and t
RMR
after the rising
edge of MR for a valid reset cycle. If reading from the FIFO
after a reset cycle is attempted, the outputs will all be in the
high-impedance state.
Note:
15. Expansion Out of device 1 (XO
1
) is connected to Expansion In of device 2 (XI
2
).
Switching Waveforms
(continued)
ExpansionTiming Diagrams
C420
–
17
R
W
XO
1
(XI
2
)
D
0
–
D
8
DATA VALID
DATA
VALID
DATA
VALID
t
XOL
t
XOH
t
HD
t
SD
t
SD
t
HD
t
XOL
t
LZR
t
A
t
DVR
t
XOH
t
A
t
DVR
t
HZR
XO
1
(XI
2
)
Q
0
–
Q
8
WRITE TO LAST PHYSICAL
LOCATION OF DEVICE 1
WRITE TO FIRST PHYSICAL
LOCATION OF DEVICE 2
READ FROM LAST PHYSICAL
LOCATION OF DEVICE 1
READ FROM FIRST PHYSICAL
LOCATION OF DEVICE 2
C420
–
18
t
WR
t
RR
DATA VALID
[15]
[15]
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| 7C420-30 | 256/512/1K/2K/4K x 9 Asynchronous FIFO |
| 7C420-40 | 256/512/1K/2K/4K x 9 Asynchronous FIFO |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 7C420-30 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:256/512/1K/2K/4K x 9 Asynchronous FIFO |
| 7C420-40 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:256/512/1K/2K/4K x 9 Asynchronous FIFO |
| 7C4205AT | 制造商:Cypress Semiconductor 功能描述: |
| 7C420-65 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:256/512/1K/2K/4K x 9 Asynchronous FIFO |
| 7C42100001 | 功能描述:42.15MHz CMOS XO (Standard) Oscillator Surface Mount 3.3V Enable/Disable 制造商:txc corporation 系列:7C 包裝:帶卷（TR） 零件狀態(tài):有效 類型:XO（標準） 頻率:42.15MHz 功能:啟用/禁用 輸出:CMOS 電壓 - 電源:3.3V 頻率穩(wěn)定度:±50ppm 工作溫度:-40°C ~ 85°C 電流 - 電源（最大值）:- 等級:- 安裝類型:表面貼裝 大小/尺寸:0.197" 長 x 0.126" 寬（5.00mm x 3.20mm） 高度:0.055"（1.40mm） 封裝/外殼:4-SMD，無引線（DFN，LCC） 電流 - 電源（禁用）（最大值）:* 標準包裝:1,000 |
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