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參數(shù)資料
| 型號： | 7C146-35 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 19.44 to 40 MHz, 3.3V, VCXO IC for General Purpose Applications |
| 中文描述： | 2Kx8雙端口靜態(tài)存儲器 |
| 文件頁數(shù)： | 8/18頁 |
| 文件大?。?/td> | 339K |
| 代理商： | 7C146-35 |
CY7C132/CY7C136
CY7C142/CY7C146
8
Write Cycle No.1 (OE Three-States Data I/Os-Either Port)
[15, 23]
Write Cycle No. 2 (R/W Three–States Data I/Os-Either Port)
[15, 24]
Notes:
23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
PWE
or t
HZWE
+ t
SD
to allow the data I/O pins to enter high impedance and for data
to be placed on the bus for the required t
.
24. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high-impedance state.
Switching Waveforms
(continued)
t
AW
t
WC
DATA VALID
HIGH IMPEDANCE
t
SCE
t
SA
t
PWE
t
HD
t
SD
t
HA
t
HZOE
CE
R/W
ADDRESS
OE
D
OUT
DATA
IN
C132-10
t
AW
t
WC
t
SCE
t
SA
t
PWE
t
HD
t
SD
t
HZWE
t
HA
HIGH IMPEDANCE
CE
R/W
ADDRESS
D
OUT
DATA
IN
t
LZWE
DATA VALID
C132-11
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