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參數(shù)資料
| 型號： | 7C132-55 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | AML32 Series, Solid State Pushbutton, Rectangular, Standard Bezel, Lighted, 1 Neon Lamp, DPST NO Form X , Alternate Action, Snap in panel mount |
| 中文描述： | 2Kx8雙端口靜態(tài)存儲器 |
| 文件頁數(shù)： | 6/18頁 |
| 文件大小： | 339K |
| 代理商： | 7C132-55 |
CY7C132/CY7C136
CY7C142/CY7C146
6
WRITE CYCLE
[15]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
BUSY/INTERRUPT TIMING
Write Cycle Time
35
45
55
ns
CE LOW to Write End
30
35
40
ns
Address Set-Up to Write End
30
35
40
ns
Address Hold from Write End
2
2
2
ns
Address Set-Up to Write Start
0
0
0
ns
R/W Pulse Width
25
30
30
ns
Data Set-Up to Write End
15
20
20
ns
Data Hold from Write End
R/W LOW to High Z
[10]
R/W HIGH to Low Z
[10]
0
0
0
ns
20
20
25
ns
0
0
0
ns
t
BLA
t
BHA
t
BLC
t
BHC
t
PS
t
WB
t
WH
t
BDD
t
DDD
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
[16]
20
25
30
ns
20
25
30
ns
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
[16]
20
25
30
ns
20
25
30
ns
Port Set Up for Priority
R/W LOW after BUSY LOW
[17]
5
5
5
ns
0
0
0
ns
R/W HIGH after BUSY HIGH
30
35
35
ns
BUSY HIGH to Valid Data
35
45
45
ns
Write Data Valid to Read Data Valid
Note
18
Note
18
Note
18
ns
t
WDD
Write Pulse to Data Delay
Note
18
Note
18
Note
18
ns
INTERRUPT TIMING
[19]
t
WINS
t
EINS
t
INS
t
OINR
t
EINR
t
INR
Notes:
11.
R/W to INTERRUPT Set Time
25
35
45
ns
CE to INTERRUPT Set Time
25
35
45
ns
Address to INTERRUPT Set Time
OE to INTERRUPT Reset Time
[16]
CE to INTERRUPT Reset Time
[16]
Address to INTERRUPT Reset Time
[16]
25
35
45
ns
25
35
45
ns
25
35
45
ns
25
35
45
ns
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
I
/I
and 30-pF load capacitance.
12. AC test conditions use V
= 1.6V and V
= 1.4V.
13. At any given temperature and voltage condition for any given device, t
is less than t
and t
is less than t
.
14. t
, t
, t
, t
t
and t
are tested with C
= 5pF as in part (b) of AC Test Loads.Transition is measured ±500 mV from steady-state voltage.
15. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
16. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
17. CY7C142/CY7C146 only.
18. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
19. 52-pin PLCC and PQFP versions only.
Switching Characteristics
Over the Operating Range
[6, 11]
(continued)
7C132-35
7C136-35
7C142-35
7C146-35
7C132-45
7C136-45
7C142-45
7C146-45
7C132-55
7C136-55
7C142-55
7C146-55
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