參數(shù)資料
型號： 7ABT543APWDH
廠商： NXP Semiconductors N.V.
英文描述： Octal latched transceiver with dual enable 3-State
中文描述： 八進制鎖存使收發(fā)器雙三態(tài)
文件頁數(shù)： 2/12頁
文件大?。?/td> 112K
代理商： 7ABT543APWDH
Philips Semiconductors
Product specification
74ABT543A
Octal latched transceiver with dual enable
(3-State)
2
1998 Sep 24
853-1794 20080
FEATURES
Combines 74ABT245 and 74ABT373 type functions in one device
8-bit octal transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each direction
Output capability: +64mA/–32mA
Live insertion/extraction permitted
Power-up 3-State
Power-up reset
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT543A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT543A Octal Registered Transceiver contains two sets of
D-type latches for temporary storage of data flowing in either
direction. Separate Latch Enable (LEAB, LEBA) and Output Enable
(OEAB, OEBA) inputs are provided for each register to permit
independent control of data transfer in either direction. The outputs
are guaranteed to sink 64mA.
FUNCTIONAL DESCRIPTION
The 74ABT543A contains two sets of eight D-type latches, with
separate control pins for each set. Using data flow from A to B as an
example, when the A-to-B Enable (EAB) input and the A-to-B Latch
Enable (LEAB) input are Low the A-to-B path is transparent. A
subsequent Low-to-High transition of the LEAB signal puts the A
data into the latches where it is stored and the B outputs no longer
change with the A inputs. With EAB and OEAB both Low, the
3-State B output buffers are active and display the data present at
the outputs of the A latches.
Control of data flow from B to A is similar, but using the EBA, LEBA,
and OEBA inputs.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
°
C; GND = 0V
TYPICAL
UNIT
t
PLH
t
PHL
C
IN
Propagation delay
An to Bn or Bn to An
Input capacitance
C
L
= 50pF; V
CC
= 5V
2.9
3.6
4
ns
V
I
= 0V or V
CC
Outputs disabled;
V
O
= 0V or V
CC
Outputs disabled; V
CC
=5.5V
pF
C
I/O
I/O capacitance
7
pF
I
CCZ
Total supply current
110
μ
A
ORDERING INFORMATION
PACKAGES
24-Pin Plastic DIP
24-Pin plastic SO
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
OUTSIDE NORTH AMERICA
74ABT543A N
74ABT543A D
74ABT543A DB
74ABT543A PW
NORTH AMERICA
74ABT543A N
74ABT543A D
74ABT543A DB
7ABT543APW DH
DWG NUMBER
SOT222-1
SOT137-1
SOT340-1
SOT355-1
PIN CONFIGURATION
24
23
22
21
20
19
18
17
16
10
15
9
8
7
6
5
4
3
2
1
V
CC
EBA
B0
B1
B2
B3
B4
B5
B6
B7
OEBA
A0
A1
A2
A3
A4
A5
A6
A7
LEBA
14
12
13
11
LEAB
OEAB
EAB
GND
SA00168
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
14, 1
LEAB / LEBA
A to B / B to A Latch Enable
input (active-Low)
11, 23
EAB / EBA
A to B / B to A Enable input
(active-Low)
13, 2
OEAB / OEBA
A to B / B to A Output Enable
input (active-Low)
3, 4, 5, 6,
7, 8, 9, 10
A0 – A7
Port A, 3-State outputs
22, 21, 20, 19,
18, 17, 16, 15
B0 – B7
Port B, 3-State outputs
12
GND
Ground (0V)
24
V
CC
Positive supply voltage
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