
Notes
79RC32438 User Reference Manual
14 - 1
November 4, 2002
Chapter 14
Counter/Timers
Functional Overview
The RC32438 contains three general purpose 32-bit counter/timers that operate at the IPBus clock
(ICLK) frequency.
Each timer/counter is composed of three registers:
The Count Register, which is a 32-bit register that holds the current value of timers. It is incre-
mented on every clock ICLK clock cycle.
The Compare Register, which is a 32-bit register that holds the value to which the count register is
compared.
The Control Register, which holds the status and control information of the counter.
Counter/Timers Register Description
Theory of Operation
A counter timer is enabled by setting the enable bit (EN) in the corresponding counter timer [0|1|2]
control (CTC[0|1|2]) register. When this occurs, the counter timer begins incrementing its current counter
timer count value with each IPBus (ICLK) clock cycle. The CPU may determine the current timer count
value by reading the corresponding counter timer [0|1|2] count (COUNT[0|1|2]) register. Writing to this
register modifies the counter timer count value. For normal operation, this register should be initialized to
zero prior to enabling a counter timer.
Register Offset
Register Name
Register Function
Size
0x02_8000
COUNT0
Counter timer 0 count
32-bit
0x02_8004
COMPARE0
Counter timer 0 compare
32-bit
0x02_8008
CTC0
Counter timer 0 control
32-bit
0x02_800C
COUNT1
Counter timer 1 count
32-bit
0x02_8010
COMPARE1
Counter timer 1 compare
32-bit
0x02_8014
CTC1
Counter timer 1 control
32-bit
0x02_8018
COUNT2
Counter timer 2 count
32-bit
0x02_801C
COMPARE2
Counter timer 2 compare
32-bit
0x02_8020
CTC2
Counter timer 2 control
32-bit
0x02_8024
RCOUNT
Refresh timer count
32-bit
0x02_8028
RCOMPARE
Refresh timer compare
32-bit
0x02_802C
RTC
Refresh timer control
32-bit
0x02_8030 through 0x02_FFFF
Reserved