參數(shù)資料
型號(hào)： 79RC32T355150DHI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 微控制器/微處理器
英文描述： Communications Processor
中文描述： 32-BIT, 150 MHz, RISC PROCESSOR, PQFP208
封裝： 28 X 28 MM, 3.40 MM HEIGHT, MO-143FA1, PLASTIC, QFP-208
文件頁(yè)數(shù)： 12/47頁(yè)
文件大小： 987K
代理商： 79RC32T355150DHI
12 of 47
May 25, 2004
IDT 79RC32355
Boot Configuration Vector
The boot configuration vector is read into the RC32355 during cold reset. The vector defines parameters in the RC32355 that are essential to oper-
ation when cold reset is complete.
The encoding of boot configuration vector is described in Table 2, and the vector input is illustrated in Figure 6.
U1CTSN
I
STI
UART channel 1 clear to send.
Primary function: General Purpose I/O, GPIOP[13]. At reset, this pin defaults to primary function GPIOP[13] if ICE Interface
enable is not selected during reset using the boot configuration.
2nd Alternate function: PC trace clock, EJTAG_DCLK.
1.
Schmitt Trigger Input.
2. 2
I
2
C - Bus Specification by Philips Semiconductors.
Signal
Name/Description
MDATA[2:0]
Clock Multiplier
. This field specifies the value by which the system clock (CLKP) is multiplied internally to generate the CPU pipeline clock.
0x0 - multiply by 2
0x1 - multiply by 3
0x2 - multiply by 4
0x3 - reserved
0x4 - reserved
0x5 - reserved
0x6 - reserved
0x7 - reserved
MDATA[3]
Endian.
This bit specifies the endianness of RC32355.
0x0 - little endian
0x1 - big endian
MDATA[4]
Reserved.
Must be set to 0.
MDATA[5]
Debug Boot Mode
. When this bit is set, the RC32355 begins executing from address 0xFF20_0200 rather than 0xBFC0_0000 following a reset.
0x0 - regular mode (processor begins executing at 0xBFC0_0000)
0x1 - debug boot mode (processor begins executing at 0xFF20_0200)
MDATA[7:6]
Boot Device Width
. This field specifies the width of the boot device.
0x0 - 8-bit boot device width
0x1 - 16-bit boot device width
0x2 - 32-bit boot device width
0x3 - reserved
MDATA[8]
EJTAG/ICE Interface Enable
. When this bit is set, Alternate 2 pin functions EJTAG_PCST[2:0], EJTAG_DCLK, and EJTAG_TRST_N are
selected.
0x0 - GPIOP[31, 13:10] pins behaves as GPIOP
0x1 - GPIOP[31] pin behaves as EJTAG_TRST_N,
GPIOP[12:10] pins behave as EJTAG_PCST[2:0], and
GPIOP[13] pin behaves as EJTAG_DCLK
MDATA[9]
Fast Reset
. When this bit is set, RC32355 drives RSTN for 64 clock cycles, used during test only. Clear this bit for normal operation.
0x0 - Normal reset: RC32355 drives RSTN for minimum of 4096 clock cycles
0x1 - Fast Reset: RC32355 drives RSTN for 64 clock cycles (test only)
MDATA[10]
DMA Debug Enable
. When this bit is set, Alternate 2 pin function, DMAP is selected. DMAP provides the DMA channel number during memory
and peripheral bus DMA transactions.
0x0 - GPIOP[8, 9, 25, 23] pins behave as GPIOP
0x1 - GPIOP[8, 9, 25, 23] pins behave as DMAP[3:0]
Table 2 Boot Configuration Vector Encoding (Part 1 of 2)
Name
Type I/O Type
Description
Table 1 Pin Descriptions (Part 8 of 8)
相關(guān)PDF資料
PDF描述
79RC32T355180DH Communications Processor
79RC32355-150DH IDT Interprise Integrated Communications Processor
79RC32355-150DHI Communications Processor
79RC32355-180DH Communications Processor
79RC32355-180DHI Communications Processor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
79RC32T355-150DHI 制造商:Integrated Device Technology Inc 功能描述:MPU RC32300 RISC 32-Bit 150MHz 3.3V 208-Pin PQFP
79RC32T355180DH 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:Communications Processor
79RC32T355-180DH 制造商:Integrated Device Technology Inc 功能描述:MPU RC32300 RISC 32-Bit 180MHz 3.3V 208-Pin PQFP
79RC32T355180DHG 制造商:Integrated Device Technology Inc 功能描述:MPU RC32300 RISC 32-Bit 180MHz 3.3V 208-Pin PQFP
79RC32T355-180DHG 制造商:Integrated Device Technology Inc 功能描述:MPU RC32300 RISC 32-Bit 180MHz 3.3V 208-Pin PQFP
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