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IDT PCI Bus Interface
PCI Register Description
79RC32438 User Reference Manual
10 - 11
November 4, 2002
Notes
Read Value:
Previous value written
Write Effect:
Modify value
NMI
Description:
Non-maskable Interrupt.
When this bit is set, the NMI bit in the PCIS register is masked from
generating an interrupt.
Initial Value:
0x1
Read Value:
Previous value written
Write Effect:
Modify value
II
Description:
Inbound Interrupt.
When this bit is set, the II bit in the PCIS register is masked from generating
an interrupt.
Initial Value:
0x1
Read Value:
Previous value written
Write Effect:
Modify value
CWE
Description:
CPU Write Error.
When this bit is set, the CWE bit in the PCIS register is masked from generat-
ing an interrupt.
Initial Value:
0x1
Read Value:
Previous value written
Write Effect:
Modify value
CRE
Description:
CPU Read Error.
When this bit is set, the CRE bit in the PCIS register is masked from generat-
ing an interrupt.
Initial Value:
0x1
Read Value:
Previous value written
Write Effect:
Modify value
MDPE
Description:
Master Data Parity Error.
When this bit is set, the MDPE bit in the PCIS register is masked from
generating an interrupt.
Initial Value:
0x1
Read Value:
Previous value written
Write Effect:
Modify value
STA
Description:
Signalled Target Abort.
When this bit is set, the STA bit in the PCIS register is masked from
generating an interrupt.
Initial Value:
0x1