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  • 參數(shù)資料
    型號(hào): 79RC32H435-350BCI
    廠商: Integrated Device Technology, Inc.
    英文描述: IDTTM InterpriseTM Integrated Communications Processor
    中文描述: IDTTM InterpriseTM集成通信處理器
    文件頁(yè)數(shù): 16/53頁(yè)
    文件大?。?/td> 444K
    代理商: 79RC32H435-350BCI
    16 of 53
    January 19, 2006
    IDT 79RC32435
    S ystem Clock Parameters
    (Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 15 and 16.)
    Figure 3 Clock Parameters Waveform
    Parameter
    S ymbol
    Referenc e
    Edge
    266MHz
    300MHz
    350MHz
    400MHz
    Units
    T iming
    Diagram
    Referenc e
    Mn
    Max
    Mn
    Max
    Min
    Max
    Mn
    Max
    PCLK
    1
    1.
    The CPU pipeline clock (PCLK) speed is selected during cold reset by the boot configuration vector (see Table 3). Refer to Chapter 3, Clocking and Initialization, in the RC32435
    User Reference Manual for the allowable frequency ranges of CLK and PCLK.
    2.
    ICLK is the internal IPBus clock. It is always equal to PCLK divided by 2. This clock cannot be sampled externally.
    3.
    The ethernet clock (MIIxRXCLK and MIIxTXCLK) frequency must be equal to or less than 1/2 ICLK (MIIxRXCLK and MIIxTXCLK <= 1/2(ICLK)).
    4.
    PCICLK must be equal to or less than two times ICLK (PCICLK <= 2(ICLK)) with a maximumPCICLK of 66 MHz.
    5.
    The input clock (CLK) is input fromthe external oscillator to the internal PLL.
    Frequency
    none
    200
    266
    200
    300
    200
    350
    200
    400
    MHz
    See Figure 3.
    Tper
    3.8
    5.0
    3.3
    5.0
    2.85
    5.0
    2.5
    5.0
    ns
    ICLK
    2,3,4
    Frequency
    none
    100
    133
    100
    150
    100
    175
    100
    200
    MHz
    Tper
    7.5
    10.0
    6.7
    10.0
    5.7
    10.0
    5.0
    10.0
    ns
    CLK
    5
    Frequency
    none
    25
    125
    25
    125
    25
    125
    25
    125
    MHz
    Tper_5a
    8.0
    40.0
    8.0
    40.0
    8.0
    40.0
    8.0
    40.0
    ns
    Thigh_5a,
    Tlow_5a
    40
    60
    40
    60
    40
    60
    40
    60
    % of
    Tper_5a
    Trise_5a,
    Tfall_5a
    3.0
    3.0
    3.0
    3.0
    ns
    Tjitter_5a
    0.1
    0.1
    0.1
    0.1
    ns
    Table 5 Clock Parameters
    Tlow_5a
    Thigh_5a
    Tper_5a
    CLK
    Trise_5a
    Tfall_5a
    Tjitter_5a
    Tjitter_5a
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