參數(shù)資料
型號(hào): 79RC32351-133DH
廠(chǎng)商: Integrated Device Technology, Inc.
英文描述: IDT Interprise Integrated Communications Processor
中文描述: IDT的洽談會(huì)集成通信處理器
文件頁(yè)數(shù): 29/42頁(yè)
文件大?。?/td> 560K
代理商: 79RC32351-133DH
29 of 42
May 25, 2004
IDT 79RC32351
Signal
Symbol
Reference
Edge
100MHz
133MHz
Unit
Conditions
Timing
Diagram
Reference
Min
Max
Min
Max
USB
USBCLKP
1
Tperiod1
none
19.79
21.87
19.79
21.87
ns
Figure 15
Thigh1,Tlow1
8.3
8.3
ns
Trise1,Tfall1
3
3
ns
Tjitter1
0.8
0.8
ns
1/4th of the minimum
Source data jitter
USBDN, USBDP
Trise2
4
20
4
20
ns
Universal Serial Bus
Specification (USBS)
Revision 1.1: Figures
7.6 and 7.7.
Tfall2
4
20
4
20
ns
USBS Revision 1.1:
Figures 7.6 and 7.7.
USBDN and USBDP Rise
and Fall Time Matching
90
111.11
90
111.11
%
USBS Revision 1.1:
Note 10, Section
7.1.2.
Data valid period
Tstate
60
60
ns
Skew between USBDN
and USBDP
0.4
0.4
ns
USBS Revision 1.1:
Section 7.1.3
Source data jitter
3.5
3.5
ns
USBS Revision 1.1:
Table 7-6
Receive data jitter
12
12
ns
Source EOP length
Tseop
160
175
160
175
ns
Receive EOP length
Treop
82
82
ns
EOP jitter
-2
5
-2
5
ns
Full-speed Data Rate
Tfdrate
11.97
12.03
11.97
12.03
MHz
Average bit rate,
USBS Section 7.1.11.
Frame Interval
0.9995 1.0005 0.9995 1.0005
ms
USBS Section 7.1.12.
Consecutive Frame Inter-
val Jitter
42
42
ns
Without frame adjust-
ment.
126
126
ns
With frame adjust-
ment.
1
USB clock (USBCLKP) frequency must be less than CLKP frequency.
Table 10 USB AC Timing Characteristics
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