2 of 30
August 31, 2004
IDT 79RC32334—Rev. Y
◆
4 DMA Channels
–
4 general purpose DMA, each with endianess swappers and
byte lane data alignment
–
Supports scatter/gather, chaining via linked lists of records
–
Supports memory-to-memory, memory-to-I/O, memory-to-
PCI, PCI-to-PCI, and I/O-to-I/O transfers
–
Supports unaligned transfers
–
Supports burst transfers
–
Programmable DMA bus transactions burst size
(up to 16 bytes)
◆
PCI Bus Interface
–
32-bit PCI, up to 66 MHz
–
Revision 2.2 compatible
–
Target or master
–
Host or satellite
–
Three slot PCI arbiter
–
Serial EEPROM support, for loading configuration registers
◆
Off-the-shelf development tools
◆
JTAG Interface (IEEE Std. 1149.1 compatible)
◆
256-ball BGA (1.0mm spacing)
◆
3.3V operation with 5V tolerant I/O
◆
EJTAG in-circuit emulator interface
Device Overview
The IDT RC32334 device is an integrated processor based on the
RC32300 CPU core. This product incorporates a high-performance, low-
cost 32-bit CPU core with functionality common to a large number of
embedded applications. The RC32334 integrates these functions to
enable the use of low-cost PC commodity market memory and I/O
devices, allowing the aggressive price/performance characteristics of
the CPU to be realized quickly into low-cost systems.
CPU Execution Core
The RC32334 integrates the RISCore32300, the same CPU core
found in the award-winning RC32364 microprocessor.
The RISCore32300 implements the Enhanced MIPS-II ISA. Thus, it
is upwardly compatible with applications written for a wide variety of
MIPS architecture processors, and it is kernel compatible with the
modern operating systems that support IDT’s 64-bit RISController
product family.
The RISCore32300 was explicitly defined and designed for inte-
grated processor products such as the RC32334. Key attributes of the
execution core found within this product include:
◆
High-speed, 5-stage scalar pipeline executes to 150MHz. This
high performance enables the RC32334 to perform a variety of
performance intensive tasks, such as routing, DSP algorithms,
etc.
◆
32-bit architecture with enhancements of key capabilities. Thus,
the RC32334 can execute existing 32-bit programs, while
enabling designers to take advantage of recent advances in
CPU architecture.
◆
Count leading-zeroes/ones. These instructions are common to a
wide variety of tasks, including modem emulation, voice over IP
compression and decompression, etc.
◆
Cache PREFetch instruction support, including a specialized
form intended to help memory coherency. System programmers
can allocate and stage the use of memory bandwidth to achieve
maximum performance.
◆
8kB of 2-way set associative instruction cache
Figure 2 RC32334 Based System Diagram
SDRAM
FLASH
Local I/O
Serial
EEPROM
Serial
Channels
Programmable I/O
RC32334
Integrated
Core
Controller
32-bit, 66MHz PCI
Local
Memory
I/O Bus