參數(shù)資料
型號: 78Q2123-DB
廠商: Maxim Integrated Products
文件頁數(shù): 25/38頁
文件大?。?/td> 0K
描述: BOARD DEMO 78Q2123 78Q2133
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
系列: *
DS_21x3_001
78Q2123/78Q2133 Data Sheet
Rev. 1.6
31
4.7.4
10BASE-T Transmitter
The Manchester-encoded data pulses, the link pulse and the start-of-idle pulse are tested against the
templates and using the procedures found in Clause 14 of IEEE 802.3.
Parameter
Condition
Min
Nom
Max
Unit
Peak Differential Output Signal
(see note below)
All data patterns
2.2
2.8
V
Harmonic Content
(dB below fundamental)
Any harmonic
All ones data
Not tested
27
dB
Link Pulse Width
100
ns
Start-of-Idle Pulse Width
Last bit 0
Last bit 1
300
350
ns
Note:
Test Condition:
Transformer P/N:
TLA-6T103
Measured at the line side of the transformer.
Line Termination:
100
±1%
4.7.5
10BASE-T Transmitter (Informative)
The specifications in the following table are included for information only. They are mainly a function of
the external transformer and termination resistors used for measurements.
Parameter
Condition
Min
Nom
Max
Unit
Output return loss
15
dB
Output Impedance Balance
1 MHz < freq < 20 MHz
29
17
10
log
f
dB
Peak Common-mode Output
Voltage
50
mV
Common-mode rejection
15 Vpk, 10.1 MHz sine wave
applied to transmitter
common-mode. All data
sequences.
100
mV
Common-mode rejection jitter
15 Vpk, 10.1 MHz sine wave
applied to transmitter
common-mode. All data
sequences.
1
ns
4.7.6
10BASE-T Receiver
Parameter
Condition
Min
Nom
Max
Unit
DLL Phase Acquisition Time
10
BT
Jitter Tolerance (pk-pk)
30
ns
Input Squelched Threshold
500
600
700
mVppd
Input Unsquelched Threshold
275
350
425
mVppd
Differential Input Resistance
20
k
Bit Error Ratio
10-10
Common-mode rejection
Square wave
0 < f < 500 kHz
Not tested
25
V
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