參數(shù)資料
型號(hào)： 78P7200L-IGT
廠商： TDK Corporation
英文描述： E3/DS3/STS-1 Transceiver
中文描述： E3/DS3/STS-1收發(fā)器
文件頁(yè)數(shù)： 1/11頁(yè)
文件大?。?/td> 171K
代理商： 78P7200L-IGT
78P7200
E3/DS3/STS-1
Line Interface Unit
DATA SHEET
Page: 1 of 11
2005 Teridian Semiconductor Corporation
Rev 3.0
JULY 2005
DESCRIPTION
The 78P7200 is a line interface transceiver IC
intended for STS-1 (51.84 Mbit/s), DS3 (44.736
Mbit/s) and E3 (34.368 Mbit/s) applications. The
receiver has a very wide dynamic range and is
designed to accept either HDB3 or B3ZS-encoded
Alternate-Mark Inversion (AMI) inputs; it provides
CMOS logic level clock, positive data, negative data
and low-level signal detector outputs. An on-chip
equalizer improves the intersymbol interference
tolerance on the receive path. The transmitter
converts CMOS logic level clock, positive data and
negative data input signals into AMI pulses of the
appropriate shape for transmission. A line buildout
(LBO) equalizer may be selected to shape the
outgoing pulses for shorter line lengths. The
78P7200 requires a single 5 volt supply and is
available in a surface mount package.
FEATURES
Single chip transmit and receive interface for
STS-1 (51.84 Mbit/s), E3 (34.368 Mbit/s) or DS3
(44.736 Mbit/s) applications
On-chip Receive Equalizer
Unique clock recovery circuit, requires no
crystals, tuned components or external clock
Selectable transmit line buildout (LBO) to
accommodate shorter line lengths
Compliant with ANSI T1.102-1993, Bellcore TR-
NWT-000499 and GR-253-CORE, ITU-T G.703
and G.823_1991
Low-level input signal indication
Available in a 28 PLCC surface mount package
-40°C to +85°C operating range
BLOCK DIAGRAM
Low-Level Signal
Detection
Clock Recovery
Data
Detection
RVcc
RFO
TVcc
OPT!
TCLK
TPOS
TNEG
DGND
RNEG
RPOS
DVcc
RCLK
LOWSIG
RLF2
Signal
Acquisition
Output
Driver,
Line
Buildout
OPT@
RLF1
LBO
Pulse
Shaper
Pulse
Generator
CLF1
RVcc
Eq.
RVcc
CPD
INPUT
OUTPUT
LIN+
LIN-
LOUT+
LOUT-
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