參數(shù)資料
型號(hào)： 78P234X
英文描述： DS3 / E3 / STS-1 Transceivers
中文描述： DS3 / E3展/ STS - 1的收發(fā)器
文件頁(yè)數(shù)： 2/3頁(yè)
文件大?。?/td> 218K
代理商： 78P234X
receive MUX that can select a
redundant channel, a clock polarity
selection mode, and the ability to
receive a DSX3 monitor signal.
STANDARDS
–
Compliant with ANSI T1.102-1993,
Telcordia GR-499-CORE and GR-
253-CORE, ITU-T G.703, G.823
and G.824 for jitter tolerance and
G.775 for loss of signal
–
Compliant with ATM FORUM af-
phy-0034 (E3 public UNI) and af-
phy-0054 (DS3 public UNI)
–
Compliant with TBR-24 1997 for E3
jitter transfer
FEATURES
78P234xJAT
–Transformer or AC-coupled
with capacitors
–Standards-based LOS
function
–Optional serial-port based
mode selection and channel
status monitoring
–Receiver AGC corrects for up
to 6dB of flat loss
–Adaptive digital clock
recovery (requires line-rate
precision reference clock
input)
–Receive output clock
maintains nominal line-rate
frequency at all times
–Fully integrated Jitter
Attenuation function provided
for all line rates (no external
VCXO required)
–Jitter Attenuator configurable
for transmit or receive path
–Transmit line fault monitor
–Requires no external current-
setting resistor or loop filter
components
–Single 3.3V supply operation
–Available in 100TQFP
The 78P234xJAT is TDK Semiconductor’s next generation of Line Interface Unit
with integrated Jitter Attenuator. It is designed and manufactured in state of the
art CMOS process technology, delivering per port the industry's lowest power
consumption line interface transceiver to the market. These devices provide the
greatest flexibility, and offer lower cost solution to the network system designer.
PRODUCT DESCRIPTION
Block Diagram
The 78P234xJAT is a low-power,
2/3/4-port DS3/E3/STS1 transceiver
IC with integrated Jitter Attenuator
(JAT). It includes clock recovery and
transmitter pulse shaping functions for
applications using 75-ohm coaxial
cable at distances up to 1200 feet long
end-to-end or up to 750ft long from a
DS3 cross connect.
The receiver recovers clock and data
from a B3ZS or HDB3 coded AMI
signal. It can compensate for over
12dB of cable and 6dB of flat loss. The
transmitter generates a signal that
meets the standard pulse shape
requirements. It has a selectable
B3ZS/HDB3 ENDEC with a receive
line code violation detector, a local and
remote loop-back mode, an input
LINN
LINP
LOUTN
LOUTP
TPOS
TNEG
TCLK
RCLK
RPOS
RNEG
DS3
TXEN
RLBKA
RLBKB
DLBK
PDTX
ENDEC
Signals from
Adjacent Port
TXNW
Control
Registers
CS
SCK
SDI
SDO
E3
LBO
Master
Bias
Generator
CKREF
Port 1
Port 2
Port 3
Port 4
CKREF
LOS
MON
Attenuator
Power
Distribution
B3ZS /
HDB3
Encoder
Data
Detector
B3ZS /
HDB3
Decoder
Adaptive
Equalizer
Signal
Detector
Transmit
Monitor
Pulse
Shaper
Controls
Jitter
Attenuator
Flags
TCLKP
RCLKP
Clock
Recovery
AGC
PDRX
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