參數(shù)資料
型號： 76132P
廠商： Intersil Corporation
英文描述： Dual, Precision JFET High Speed Operational Amplifier; Package: SOIC; No of Pins: 8; Temperature Range: Industrial
中文描述： 第75A，30V的，0.011 Ohm的N通道，邏輯電平UltraFET功率MOSFET
文件頁數(shù)： 6/10頁
文件大?。?/td> 110K
代理商： 76132P
6-135
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
Typical Performance Curves
Unless Otherwise Specified
(Continued)
C
OSS
2500
1500
0
0
5
15
25
C
2000
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
1000
30
500
C
ISS
C
RSS
10
20
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
≈
C
DS
+ C
GD
10
8
6
4
0
V
G
,
V
DD
= 15V
2
30
50
0
Q
g
, GATE CHARGE (nC)
10
I
D
= 75A
I
D
= 51A
I
D
= 25A
WAVEFORMS IN
DESCENDING ORDER:
20
40
100
20
30
40
50
0
400
300
200
0
10
S
R
GS
, GATE TO SOURCE RESISTANCE (
)
V
GS
= 4.5V, V
DD
= 15V, I
D
= 41A, R
L
= 0.312
t
d(OFF)
t
d(ON)
t
r
t
f
20
30
40
50
0
400
200
100
0
10
S
R
GS
, GATE TO SOURCE RESISTANCE (
)
V
GS
= 10V, V
DD
= 15V, I
D
= 75A, R
L
= 0.20
300
t
r
t
f
t
d(OFF)
t
d(ON)
t
P
V
GS
0.01
L
I
AS
+
-
V
DS
V
DD
R
G
DUT
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
HUF76132P3, HUF76132S3S
相關(guān)PDF資料
PDF描述
76132P 75A, 30V, 0.011 Ohm, N-Channel, Logic Level UltraFET Power MOSFETs
F10-SERIES TPS65124 Evaluation Module
F12-SERIES Peripheral IC
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