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參數(shù)資料
| 型號： | 7542 |
| 英文描述： | 250mA CMOS LDO, lsupply 1uA and 2% Vout Accuracy, -40C to +125C, 3-SOT-23, T/R |
| 中文描述： | 7542群時鐘異步串行I / OApplication注意70K/MAY.22.03 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 70K |
| 代理商： | 7542 |
May 2003
7542 Group
Clock Asynchronous Serial I/O (UART)
Page 7 of 8
REJ05B0023-0100Z
Figure 6 Control procedure of receiver
0
0
Y
RESET
1 0 1
1
UART1CON(Address 1B
16
)
0
1
0
16
)
BRG(Address 1C
16
)
“07
16
”
N
N
Y
N
N
Y
Y
N
Y
Error processing
SEI
CLD
CLT
SIO1CON(Address 1A
16
)
BRG count source: f(X
IN
)/4
Synchronous clock:
BRG output/16
Transmit disabled
Receive enabled
UART
Serial I/O1 enabled
Set serial I/O1 control register
Initialization
Character length: 8 bits
Parity disabled
Stop bit length: 2 bits
Set UART1 control register
Set baud rate generator1
TB1/RB1(Address 18
16
)
Read the first-byte transmission data from
the transmit/receive buffer register1
Receive buffer is full
(checked by b1 of SIO1STS
(address 19
16
))
Communication control port P0
0
= “0”
Set the communication control port P0
0
to the
input mode.
TB1/RB1(Address 18
16
)
Read the second-byte transmission data from
the transmit/receive buffer register1
Error occurs
(checked by b6 of SIO1STS
(address 19
16
))
Error occurs
(checked by b6 of SIO1STS
(address 19
16
))
Receive buffer is full
(checked by b1 of SIO1STS
(address 19
16
))
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