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參數(shù)資料
| 型號： | 74VHC221ASJX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | MULTIVIBRATOR DUAL MONO 16SOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | 74VHC |
| 邏輯類型： | 單穩(wěn)態(tài) |
| 獨(dú)立電路： | 2 |
| 施密特觸發(fā)器輸入： | 無 |
| 傳輸延遲： | 8.1ns |
| 輸出電流高，低： | 8mA，8mA |
| 電源電壓： | 2 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOP |
| 包裝： | 帶卷 (TR) |
74VHC221A
Dual
Non-Retrig
g
erab
le
Monostab
le
Multivibrator
1994 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74VHC221A Rev. 1.2
4
Functional Description
1. Stand-by State
The external capacitor (Cx) is fully charged to VCC in
the Stand-by State. That means, before triggering,
the QP and QN transistors which are connected to the
Rx/Cx node are in the off state. Two comparators that
relate to the timing of the output pulse, and two refer-
ence voltage supplies turn off. The total supply cur-
rent is only leakage current.
2. Trigger Operation
Trigger operation is effective in any of the following
three cases. First, the condition where the A input is
LOW, and B input has a rising signal; second, where
the B input is HIGH, and the A input has a falling sig-
nal; and third, where the A input is LOW and the B
input is HIGH, and the CLR input has a rising signal.
After a trigger becomes effective, comparators C1
and C2 start operating, and QN is turned on. The
external capacitor discharges through QN. The volt-
age level at the Rx/Cx node drops. If the Rx/Cx volt-
age level falls to the internal reference voltage VrefL,
the output of C1 becomes LOW. The flip-flop is then
reset and QN turns off. At that moment C1 stops but
C2 continues operating.
After QN turns off, the voltage at the Rx/Cx node
starts rising at a rate determined by the time constant
of external capacitor Cx and resistor Rx.
Upon triggering, output Q becomes HIGH, following
some delay time of the internal F/F and gates. It stays
HIGH even if the voltage of Rx/Cx changes from fall-
ing to rising. When Rx/Cx reaches the internal refer-
ence voltage VrefH, the output of C2 becomes LOW,
the output Q goes LOW and C2 stops its operation.
That means, after triggering, when the voltage level
of the Rx/Cx node reaches VrefH, the IC returns to its
MONOSTABLE state.
With large values of Cx and Rx, and ignoring the dis-
charge time of the capacitor and internal delays of
the IC, the width of the output pulse, tW (OUT), is as
follows:
tW (OUT) = 1.0 Cx Rx
3. Reset Operation
In normal operation, the CLR input is held HIGH. If
CLR is LOW, a trigger has no affect because the Q
output is held LOW and the trigger control F/F is
reset. Also, Qp turns on and Cx is charged rapidly to
VCC.
This means if CLR is set LOW, the IC goes into a wait
state.
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