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參數(shù)資料
| 型號(hào)： | 74VHC175SJX |
| 廠商： | Fairchild Semiconductor |
| 文件頁(yè)數(shù)： | 2/9頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FLIP FLOP QUAD D TYPE 16SOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | 74VHC |
| 功能： | 主復(fù)位 |
| 類型： | D 型總線 |
| 輸出類型： | 差分 |
| 元件數(shù)： | 1 |
| 每個(gè)元件的位元數(shù)： | 4 |
| 頻率 - 時(shí)鐘： | 210MHz |
| 延遲時(shí)間 - 傳輸： | 4.9ns |
| 觸發(fā)器類型： | 正邊沿 |
| 輸出電流高，低： | 8mA，8mA |
| 電源電壓： | 2 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.209"，5.30mm 寬） |
| 包裝： | 帶卷 (TR) |
74VHC175
Quad
D-T
ype
Flip-Flop
1993 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74VHC175 Rev. 1.2
2
Logic Symbol
IEEE/IEC
Functional Description
The VHC175 consists of four edge-triggered D flip-flops
with individual D inputs and Q and Q outputs. The Clock
and Master Reset are common. The four flip-flops will
store the state of their individual D inputs on the LOW-to-
HIGH clock (CP) transition, causing individual Q and Q
outputs to follow. A LOW input on the Master Reset (MR)
will force all Q outputs LOW and Q outputs HIGH inde-
pendent of Clock or Data inputs. The VHC175 is useful
for general logic applications where a common Master
Reset and Clock are acceptable.
Truth Table
H
= HIGH Voltage Level
L
= LOW Voltage Level
tn = Bit Time before Clock Pulse
tn+1 = Bit Time after Clock Pulse
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
Inputs @ tn,
MR
= H
Outputs @ tn+1
Dn
Qn
LL
H
HH
L
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| 74VHC20MTR | 功能描述:邏輯門 Dual 4-Input NAND RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
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