參數(shù)資料
型號: 74VHC164SJ
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Quadruple 2-Input Positive-NOR Gates 14-TSSOP -40 to 85
中文描述: AHC/VHC/H/U/V SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO14
封裝: 5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-14
文件頁數(shù): 2/7頁
文件大小: 83K
代理商: 74VHC164SJ
www.fairchildsemi.com
2
7
Functional Description
The VHC164 is an edge-triggered 8-bit shift register with
serial data entry and an output from each of the eight
stages. Data is entered serially through one of two inputs
(A or B); either of these inputs can be used as an active
High Enable for data entry through the other input. An
unused input must be tied HIGH.
Each LOW-to-HIGH transition on the Clock (CP) input
shifts data one place to the right and enters into Q
0
the log-
ical AND of the two data inputs (A B) that existed before
the rising clock edge. A LOW level on the Master Reset
(MR) input overrides all other inputs and clears the register
asynchronously, forcing all Q outputs LOW.
Function Table
H
=
HIGH Voltage Levels
L
=
LOW Voltage Levels
X
=
Immaterial
Q
=
Lower case letters indicate the state of the referenced input or output
one setup time prior to the LOW-to-HIGH clock transition.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Operating
Inputs
Outputs
Mode
MR
A
B
Q
0
Q
1
–Q
7
Reset (Clear)
L
X
X
L
L–L
Shift
H
L
L
L
Q
0
–Q
6
Q
0
–Q
6
Q
0
–Q
6
Q
0
–Q
6
H
L
H
L
H
H
L
L
H
H
H
H
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