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參數(shù)資料
| 型號： | 74VHC163 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quadruple 2-Input Positive-NOR Gates 14-SOIC -40 to 85 |
| 中文描述： | AHC/VHC SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 123K |
| 代理商： | 74VHC163 |
5
www.fairchildsemi.com
7
AC Electrical Characteristics
Note 4:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: I
CC
(opr)
=
C
PD
* V
CC
* f
IN
+
I
CC
.
When the outputs drive a capacitive load, total current consumption is the sum of C
PD
, and
I
CC
which is obtained from the following formula:
C
Q0
–
C
Q3
and C
TC
are the capacitances at Q0
–
Q3 and TC, respectively. F
CP
is the input frequency of the CP.
Symbol
Parameter
V
CC
(V)
T
A
=
25
°
C
Typ
8.3
10.8
4.9
T
A
=
40
°
to
+
85
°
C
Min
1.0
1.0
1.0
Units
Conditions
Min
Max
12.8
16.3
8.1
Max
15.0
18.5
9.5
t
PLH
t
PHL
Propagation Delay
Time (CP
–
Q
n
)
3.3
±
0.3
ns
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
V
CC
=
Open
5.0
±
0.5
ns
6.4
8.7
11.2
10.1
13.6
17.1
1.0
1.0
1.0
11.5
16.0
19.5
t
PLH
t
PHL
Propagation Delay
Time (CP
–
TC, Count)
3.3
±
0.3
ns
5.0
±
0.5
4.9
6.4
11.0
8.1
10.1
17.2
1.0
1.0
1.0
9.5
11.5
20.0
ns
t
PLH
t
PHL
Propagation Delay
3.3
±
0.3
ns
Time (CP
–
TC, Load)
13.5
6.2
7.7
20.7
10.3
12.3
1.0
1.0
1.0
23.5
12.0
14.0
5.0
±
0.5
ns
t
PLH
t
PHL
Propagation Delay
Time (CET
–
TC)
3.3
±
0.3
7.5
10.5
4.9
12.3
15.8
8.1
1.0
1.0
1.0
14.5
18.0
9.5
ns
5.0
±
0.5
ns
6.4
130
85
10.1
1.0
70
50
11.5
f
MAX
Maximum Clock
Frequency
3.3
±
0.3
80
55
MHz
5.0
±
0.5
135
95
185
125
4
115
85
MHz
C
IN
C
PD
Input Capacitance
10
10
pF
Power Dissipation
Capacitance
23
pF
(Note 4)
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