參數(shù)資料
型號: 74VHC139SJ
廠商: Fairchild Semiconductor
文件頁數(shù): 2/6頁
文件大?。?/td> 0K
描述: DECODER/DEMUX DUAL 2-4 16SOP
標(biāo)準(zhǔn)包裝: 47
系列: 74VHC
類型: 解碼器/多路分解器
電路: 1 x 2:4
獨(dú)立電路: 2
輸出電流高,低: 8mA,8mA
電壓電源: 單電源
電源電壓: 2 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOP
包裝: 管件
www.fairchildsemi.com
2
74
V
HC139
Logic Symbols
IEEE/IEC
Functional Description
The VHC139 is a high-speed dual 2-to-4 decoder/demulti-
plexer. The device has two independent decoders, each of
which accepts two binary weighted inputs (A0–A1) and pro-
vides four mutually exclusive active-LOW outputs (O0–O3).
Each decoder has an active-LOW enable (E). When E is
HIGH all outputs are forced HIGH. The enable can be used
as the data input for a 4-output demultiplexer application.
Each half of the VHC139 generates all four minterms of
two variables. These four minterms are useful in some
applications, replacing multiple gate functions as shown in
Figure 1, and thereby reducing the number of packages
required in a logic network.
FIGURE 1. Gate Functions (Each Half)
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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