參數(shù)資料
型號: 74VHC03T
廠商: 意法半導(dǎo)體
英文描述: Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SSOP -40 to 85
中文描述: 四2輸入與非門開漏
文件頁數(shù): 1/7頁
文件大小: 54K
代理商: 74VHC03T
74VHC03
QUAD 2-INPUT OPEN DRAIN NAND GATE
PRELIMINARY DATA
June 1999
I
HIGHSPEED:t
PD
=3.7ns(TYP.)atV
CC
= 5V
I
LOWPOWERDISSIPATION:
I
CC
=2
μ
A(MAX.) at T
A
=25
o
C
I
HIGHNOISEIMMUNITY:
V
NIH
= V
NIL
=28%V
CC
(MIN.)
I
POWERDOWN PROTECTIONON INPUTS
I
OPERATINGVOLTAGERANGE:
V
CC
(OPR)= 2Vto 5.5V
I
PINANDFUNCTION COMPATIBLEWITH
74SERIES03
I
IMPROVEDLATCH-UP IMMUNITY
I
LOWNOISE:V
OLP
= 0.8V(Max.)
DESCRIPTION
The 74VHC03 is an advancedhigh-speed CMOS
QUAD 2-INPUT OPEN DRAIN NAND GATE
fabricated with sub-micron silicon gate
double-layermetal wiring C
2
MOS technology.
The internal circuit is composed of 3 stages
including buffer output, which provides high noise
immunity and stable output.
This device can, with an external pull-up resistor,
and
be used in wired AND configuration. This device
can also be used as a led driver and in any other
applicationrequiring a currentsink.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface5V to 3V.
All
inputs
and
outputs are
protection circuits against static discharge, giving
them 2kV ESD immunity and transient excess
voltage.
equipped with
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES :
74VHC03M
74VHC03T
M
(Micro Package)
T
(TSSOPPackage)
1/7
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