參數(shù)資料
型號: 74VCX86MTC
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Low Voltage Quad 2-Input Exclusive-OR Gate with 3.6V Tolerant Inputs and Outputs
中文描述: ALVC/VCX/A SERIES, QUAD 2-INPUT XOR GATE, PDSO14
封裝: 4.40 MM, MO-153AB, TSSOP-14
文件頁數(shù): 4/10頁
文件大?。?/td> 530K
代理商: 74VCX86MTC
www.fairchildsemi.com
4
7
DC Electrical Characteristics
(Continued)
AC Electrical Characteristics
(Note 5)
Note 5:
For C
L
50
P
F, add approximately 300 ps to the AC maximum specification.
Note 6:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Symbol
Parameter
Conditions
V
CC
(V)
Min
Max
Units
V
OL
LOW Level Output Voltage
I
OL
100
P
A
I
OL
12 mA
I
OL
18 mA
I
OL
24 mA
I
OL
100
P
A
I
OL
12 mA
I
OL
18 mA
I
OL
100
P
A
I
OL
6 mA
I
OL
100
P
A
I
OL
2 mA
I
OL
100
P
A
0
d
V
I
d
3.6V
0
d
(V
I
, V
O
)
d
3.6V
V
I
V
CC
or GND
V
CC
d
(V
I
)
V
IH
V
CC
0.6V
2.7 - 3.6
2.7
0.2
0.4
V
3.0
3.0
0.4
0.55
0.2
2.3 - 2.7
2.3
2.3
0.4
0.6
0.2
1.65 - 2.3
1.65
1.4 - 1.6
1.4
0.3
0.2
0.35
1.2
0.05
r
5.0
10
I
I
I
OFF
I
CC
Input Leakage Current
Power-OFF Leakage Current
1.2 - 3.6
0
P
A
P
A
Quiescent Supply Current
1.2 - 3.6
1.2 - 3.6
2.7 - 3.6
20
r
20
750
P
A
'
I
CC
Increase in I
CC
per Input
P
A
Symbol
Parameter
Conditions
V
CC
(V)
T
A
40
q
C to 85
q
C
Min
0.6
0.8
1.0
Units
Figure
Max
3.0
3.9
7.8
Number
t
PHL
t
PLH
Propagation Delay
C
L
30 pF, R
L
500
:
3.3
r
0.3
2.5
r
0.2
1.8
r
0.15
ns
Figures
1, 2
C
L
15 pF, R
L
2k
:
1.5
r
0.1
1.2
3.3
r
0.3
1.0
1.5
15.6
39
0.5
Figures
3, 4
t
OSHL
t
OSLH
Output to Output Skew
C
L
30 pF, R
L
500
:
ns
(Note 6)
2.5
r
0.2
1.8
r
0.15
1.5
r
0.1
0.5
0.75
1.5
C
L
15 pF, R
L
2k
:
1.2
1.5
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