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參數(shù)資料
| 型號： | 74VCX245WMX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANSCVR BIDIRECT LV 20SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 74VCX |
| 邏輯類型： | 收發(fā)器，非反相 |
| 元件數(shù)： | 1 |
| 每個(gè)元件的位元數(shù)： | 8 |
| 輸出電流高，低： | 24mA，24mA |
| 電源電壓： | 1.4 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | 74VCX245WMXDKR |
7
INDUSTRIAL TEMPERATURERANGE
IDT72V73260 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
TABLE 4 — INTERNAL REGISTER AND ADDRESS MEMORY MAPPING
TABLE 3 — OUTPUT HIGH-IMPEDANCE CONTROL
TABLE — 1 CONSTANT THROUGHPUT
DELAY VALUE
TABLE 2 — VARIABLE THROUGHPUT
DELAY VALUE
Delay for Constant Throughput Delay Mode
Input Rate
(m – output channel number)
(n – input channel number)
32.768Mb/s
512 + (512 -n) +m time-slots
Delay for Variable Throughput Delay Mode
Input Rate
(m – output channel number; n – input channel number)
m
≤≤≤≤≤ n+2
m > n+2
32.768Mb/s
512 - (n-m) time-slots
(m-n)time-slots
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
R/W
Location
1
STA4
STA3
STA2
STA1
STA0
CH8
CH7
CH6
CH5
CH4
CH3
CH2 CH1 CH0
R
Data Memory
1
0
STA4
STA3
STA2
STA1
STA0
CH8
CH7
CH6
CH5
CH4
CH3
CH2 CH1 CH0
R/W
Connection Memory
0
1
0
x
R/W
ControlRegister
0
1
0
1
x
R
Frame Align Register
0
1
0
x
R/W
Frame Offset Register 0
0
1
0
1
x
R/W
Frame Offset Register 1
0
1
0
1
0
x
R/W
Frame Offset Register 2
0
1
0
1
x
R/W
Frame Offset Register 3
0
1
0
x
R/W
Frame Offset Register 4
0
1
0
1
x
R/W
Frame Offset Register 5
0
1
0
x
R/W
Frame Offset Register 6
0
1
x
R/W
Frame Offset Register 7
Bits MOD1-0 Values in
ODE pin
OSB bit in Control
Output Status
Connection Memory
Register
1 and 1
Don’t Care
Per-channel
high-Impedance
Any, other than 1 and 1
0
high-Impedance
Any, other than 1 and 1
0
1
Enable
Any, other than 1 and 1
1
0
Enable
Any, other than 1 and 1
1
Enable
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