參數(shù)資料
型號: 74VCX16841MTD
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Low Voltage 20-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs
中文描述: ALVC/VCX/A SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56
封裝: 6.10 MM, MO-153, TSSOP-56
文件頁數(shù): 2/7頁
文件大?。?/td> 65K
代理商: 74VCX16841MTD
www.fairchildsemi.com
2
7
Connection Diagram
Truth Tables
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial (HIGH or LOW, inputs may not float)
Z
=
High Impedance
O
0
=
Previous O
0
before HIGH-to-LOW of Latch Enable
Functional Description
The 74VCX16841 contains twenty D-type latches with 3-
STATE outputs. The device is byte controlled with each
byte functioning identically, but independent of the other.
Control pins can be shorted together to obtain full 20-bit
operation. The following description applies to each byte.
When the Latch Enable (LE
n
) input is HIGH, data on the D
n
enters the latches. In this condition the latches are trans-
parent, i.e., a latch output will change states each time its
D-type input changes. When LE
n
is LOW, the latches store
information that was present on the D-type inputs a setup
time preceding the HIGH-to-LOW transition on LE
n
. The 3-
STATE outputs are controlled by the Output Enable (OE
n
)
input. When OE
n
is LOW the standard outputs are in the 2-
state mode. When OE
n
is HIGH, the standard outputs are
in the high impedance mode but this does not interfere with
entering new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs
Outputs
LE
1
OE
1
D
0
–D
9
O
0
–O
9
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O
0
Inputs
Outputs
LE
2
OE
2
D
10
–D
19
O
10
–O
19
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O
0
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