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參數(shù)資料
| 型號(hào)： | 74VCX163245GX |
| 廠商： | Fairchild Semiconductor |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | TXRX TRANSLAT 16BIT DUAL 54FBGA |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | 74VCX |
| 邏輯功能： | 變換器，3 態(tài) |
| 位數(shù)： | 16 |
| 輸入類型： | 電壓 |
| 輸出類型： | 電壓 |
| 通道數(shù)： | 2 |
| 輸出/通道數(shù)目： | 8 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 傳輸延遲（最大）： | 4.4ns |
| 電源電壓： | 1.65 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 54-FBGA |
| 供應(yīng)商設(shè)備封裝： | 54-FBGA |
| 包裝： | 帶卷 (TR) |
74VCX163245
Lo
w
V
olta
g
e
16-Bit
Dual
Suppl
y
T
ranslating
T
ransceiver
with
3-ST
A
TE
Outputs
2000 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74VCX163245 Rev. 1.7
3
Truth Tables
H
= HIGH Voltage Level
L
= LOW Voltage Level
X
= Immaterial (HIGH or LOW, inputs may not float)
Z
= High Impedance
VCX163245 Translator Power Up Sequence Recommendations
To guard against power up problems, some simple
guidelines need to be adhered to. The VCX163245 is
designed so that the control pins (T/Rn, OEn) are sup-
plied by VCCB. Therefore the first recommendation is to
begin by powering up the control side of the device,
VCCB. The OEn control pins should be ramped with or
ahead of VCCB, this will guard against bus contentions
and oscillations as all A Port and B Port outputs will be
disabled. To ensure the high impedance state during
power up or power down, OEn should be tied to VCCB
through a pull up resistor. The minimum value of the
resistor is determined by the current sourcing capability
of the driver. Second, the T/Rn control pins should be
placed at logic LOW (0V) level, this will ensure that the
B-side bus pins are configured as inputs to help guard
against bus contention and oscillations. B-side Data
Inputs should be driven to a valid logic level (0V or
VCCB), this will prevent excessive current draw and oscil-
lations. VCCA can then be powered up after VCCB, how-
ever VCCA must be greater than or equal to VCCB to
ensure proper device operation. Upon completion of
these steps the device can then be configured for the
users desired operation. Following these steps will help
to prevent possible damage to the translator device as
well as other system components.
Logic Diagrams
Please note that these diagrams are provided only for the understanding of logic operations and should not be used
to estimate propagation delays.
Inputs
Outputs
OE1
T/R1
LL
Bus B0–B7 Data to Bus A0–A7
LH
Bus A0–A7 Data to Bus B0–B7
HX
HIGH Z State on A0–A7, B0–B7
Inputs
Outputs
OE2
T/R2
LL
Bus B8–B15 Data to Bus A8–A15
LH
Bus A8–A15 Data to Bus B8–B15
HX
HIGH-Z State on A8–A15, B8–B15
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