參數(shù)資料
型號： 74V2T70STR
廠商： 意法半導(dǎo)體
英文描述： TRIPLE BUFFER
中文描述： 3個緩沖器
文件頁數(shù)： 1/7頁
文件大小： 124K
代理商： 74V2T70STR
1/7
June 2003
I
HIGH SPEED: t
PD
= 3.6ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 1
μ
A(MAX.) at T
A
= 25°C
COMPATIBLE WITH TTL OUTPUTS:
V
IH
= 2V (MIN), V
IL
= 0.8V (MAX)
POWER DOWN PROTECTION ON INPUT
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8mA (MIN) at V
CC
= 4.5V
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
IMPROVED LATCH-UP IMMUNITY
I
I
I
I
I
I
I
DESCRIPTION
The 74V2T70 is an advanced high-speed CMOS
TRIPLE BUFFER fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology.
The internal circuit is composed of 2 stages
including buffer output, which provide high noise
immunity and stable output.
Power down protection is provided on input and 0
to 7V can be accepted on input with no regard to
the supply voltage. This device can be used to
interface 5V to 3V.
74V2T70
TRIPLE BUFFER
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
T & R
SOT23-8L
74V2T70STR
SOT23-8L
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