參數(shù)資料
型號: 74LVX125
廠商: Fairchild Semiconductor Corporation
英文描述: Low Voltage Quad Buffer with 3-STATE Outputs
中文描述: 低電壓四緩沖器具有三態(tài)輸出
文件頁數(shù): 1/12頁
文件大?。?/td> 227K
代理商: 74LVX125
1/12
August 2004
I
HIGH SPEED: t
PD
=4.4ns (TYP.) at V
CC
= 3.3V
5V TOLERANT INPUTS
POWER-DOWN PROTECTION ON INPUTS
INPUT VOLTAGE LEVEL:
V
IL
= 0.8V, V
IH
= 2V at V
CC
=3V
LOW POWER DISSIPATION:
I
CC
= 2
μ
A (MAX.) at T
A
=25°C
LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
=3.3V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4 mA (MIN) at V
CC
=3V
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 125
IMPROVED LATCH-UP IMMUNITY
I
I
I
I
I
I
I
I
I
I
DESCRIPTION
The 74LVX125 is a low voltage CMOS QUAD
BUS BUFFERs fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
This device requires the 3-STATE control input G
to be set high to place the output into the high
impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V. It combines high speed
performance with the true CMOS low power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVX125
LOW VOLTAGE QUAD BUS BUFFERS (3-STATE)
WITH 5V TOLERANT INPUTS
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE
T & R
SOP
TSSOP
74LVX125MTR
74LVX125TTR
TSSOP
SOP
Rev. 3
相關PDF資料
PDF描述
74LVX125M Low Voltage Quad Buffer with 3-STATE Outputs
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相關代理商/技術參數(shù)
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