- 您現(xiàn)在的位置：買賣IC網 > PDF目錄375085 > 74LVX112SJ (FAIRCHILD SEMICONDUCTOR CORP) Low Voltage Dual J-K Flip-Flops with Preset and Clear PDF資料下載
參數資料
| 型號： | 74LVX112SJ |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low Voltage Dual J-K Flip-Flops with Preset and Clear |
| 中文描述： | LV/LV-A/LVX/H SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 封裝： | 5.30 MM, EIAJ TYPE2, SOP-16 |
| 文件頁數： | 1/7頁 |
| 文件大?。?/td> | 77K |
| 代理商： | 74LVX112SJ |
2003 Fairchild Semiconductor Corporation
DS012158
www.fairchildsemi.com
October 1996
Revised December 2003
7
74LVX112
Low Voltage Dual J-K Flip-Flops with Preset and Clear
General Description
The LVX112 is a dual J-K Flip-Flop where each flip-flop has
independent inputs (J, K, PRESET, CLEAR, and CLOCK)
and outputs (Q, Q). These devices are edge sensitive and
change states synchronously on the negative going transi-
tion of the clock pulse. Triggering occurs at a voltage level
of the clock and is not directly related to the transition time.
Clear and Preset are independent of the clock and are
accomplished by a low logic level on the corresponding
input. The J and K inputs can change when the clock is in
either state without affecting the flip-flop, provided that they
are in the desired state during the recommended setup and
hold times relative to the falling edge of the clock.
The inputs tolerate voltages up to 7V allowing the interface
of 5V systems to 3V systems.
Features
I
Input voltage level translation from 5V–3V
I
Ideal for low power/low noise 3.3V applications
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter
“
X
”
to the ordering code.
Connection Diagram
Pin Descriptions
Order Number
74LVX112M
74LVX112SJ
74LVX112MTC
Package Number
M16A
M16D
MTC16
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names
Description
J
1
, J
2
, K
1
, K
2
CLK
1
, CLK
2
CLR
1
, CLR
2
PR
1
, PR
2
Q
1
, Q
2
, Q
1
, Q
2
Data Inputs
Clock Pulse Inputs (Active Falling edge)
Direct Clear Inputs (Active LOW)
Direct Preset Inputs (Active LOW)
相關PDF資料 |
PDF描述 |
|---|---|
| 74LVX132 | Low Voltage Quad 2-Input NAND Schmitt Trigger |
| 74LVX132M | Low Voltage Quad 2-Input NAND Schmitt Trigger |
| 74LVX132MTC | Low Voltage Quad 2-Input NAND Schmitt Trigger |
| 74LVX132SJ | Low Voltage Quad 2-Input NAND Schmitt Trigger |
| 74LVX132MTCX_NL | Low Voltage Quad 2-Input NAND Schmitt Trigger |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 74LVX112SJ_Q | 功能描述:觸發(fā)器 Dual J-K Flip-Flop RoHS:否 制造商:Texas Instruments 電路數量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74LVX112SJX | 功能描述:觸發(fā)器 Dual J-K Flip-Flop RoHS:否 制造商:Texas Instruments 電路數量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74LVX125ATTR | 制造商:STMicroelectronics 功能描述:QUAD BUS BUFFER - Tape and Reel |
| 74LVX125M | 功能描述:緩沖器和線路驅動器 Quad Buffer RoHS:否 制造商:Micrel 輸入線路數量:1 輸出線路數量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| 74LVX125M | 制造商:Fairchild Semiconductor Corporation 功能描述:IC 74LVX SMD 74LVX125 SOIC14 |
發(fā)布緊急采購，3分鐘左右您將得到回復。